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Is it possible to implement Sense Amplifier in Digital?

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ajhunt18

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I'm having a thesis about SRAM designing implemented in digital. I have a problem implementing the sense amplifier in digital. Is it possible or is there a way to implement an amplifier digitally? Thanks!:smile:
 

it depends on speed/technology tradeoff. Sense amplifier allow to make a decision regarding bit value before a bitlines voltages became stable. This reduce delay and current consumption. If speed/power consumption recuirements are not a stringent for your technology node, then an even digital buffer can serve as sense amplifier.
 

I am not very familiar with this specifications of SRAM yet because I am self-studying this one. BTW, this will be my undergrad thesis (I am still a 5th year Electronics Engg student). This will be a challenge for me because as I have researched for references, all of them were implemented in analog. I haven't seen any digitally implemented SRAM so far. I will be using Synopsys VCS and my proposed topic will be A high-density, Low-leakage 4Kb 4T SRAM using NWL scheme for low-power, stand alone applications. I will be using TSMC 90nm technology.

So, should I use that Even Digital Buffer instead?

Thanks or your response! :smile:
 

you can try something like in figure. But take into account that it will worse in any case than typical SA.
 

Ah okay, do you have a reference for this diagram? So that I could read further.

Thank You!
 

I dont have reference, this is just logical "model" of sense amplifier. Typically no one commertial SRAM will not use something another, than analog SA, because penalty is speed, power consumption, reliability. Typical SA is designed in analog manner with carefull analog simulation of all corners timing, proper choice of transistor sizes (not minimal) to minimize offset, parasitics, using manualy optimized layout,... Above digital SA can be used if speed requirements are relaxed by a few times, comparing with custom designed analog SA.
 

SRAM have digital FF's as storage elements. In so far I don't understand, where you see the need for a sense amplifier? Please clarify.
 

behaviour of SRAM FF during reading data is typically transient process, where precharged bitline is going to it's stable value. Decision of bit's value is doing during this transient, as fast as possible, by regenerative Sense Amplifier typically. SRAM design/optimization looks more analog than digital to provide maximum speed/consumption tradeoff.
 

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for a some SRAM configurations a bit line's voltage changing even don't have full supply swing
 
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