Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.
Slew nothing but the transition time. You've to fix the transition violation, otherwise the tool won't be able to get the correct delay from the .lib.
If you open the .lib file, you can find a delay table.X-axis (Output cap) & Y-axis Input transition. If any of these values goes beyond the table value, then the tool extrapolates the delay value & this delay value may not be correct. In such case, your chip may not work as expected.
If setup time is met , 50% of issue is solved. With slew being very high , this net is prone to crosstalk violations. Once you enable crosstalk analysis in STA , these endpoints will start violating setup
both of setup and hold gets affected.
Cell delay is defined in a timing arc which is a 2 dimensional array,with a transition time on one axis, and output load on another. if the path has a slew that exceeds the transition time range in the timing arc, the STA tool extrapolates the timing arc to calculate the cell delay which results in the inaccurate delay. You can only trust the timing calculated by the interpolation of the timing arc. Extrapolation makes the timing inaccurate.
This site uses cookies to help personalise content, tailor your experience and to keep you logged in if you register.
By continuing to use this site, you are consenting to our use of cookies.
