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Looks like a homework problem, so I'll just point you in the right direction.
First, figure out your maximum window of operation (hint: what's the period of a 100 MHz signal)
Second, take that time (Tmax), and add up all of your delays: data transit time across the flip-flop, time(s) needed to set up the incoming signal, time(s) needed to hold data on flop. The the remainder will be the extra that can be allocated to the circuit between your flip-flops.
Its easy to give away the answer so as enjunear showed...
datapath delay < clockpath delay
So understand which is the datapath and which is the clockpath...and what are the delays in these paths...your problem solved.
Setup: min amt of time for which data should be stable before the arrival of the sensitive edge of clock....
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