mismatch reduction in cmos process

if i use common centroid approach for elimination of systemnatic mismatch, how does it affect random mismatch. In my views, it will increase random mismatch, as we are decreasing the size while using common centroid approach, because instead of taking big one capacitor, we are now taking array of small sized capacitors.can anybody clear this to me?

In general, basic statistics apply.
lim(n->inf)E(x_bar)=x_bar

And we are not only applying to common centroid. The very fact that you use large numbers will improve random mismatch.

plz clear this thing to some more extant

thanx for valuable information, but now another doubt arises. Does it mean that common centroid approach not only improves systematic mismatch, but also reduces random fluctuations.
According to pelgrom model-for equal distances, if no of samples are taken , then it follows a linear curve b/w sqrt(mismatch) and 1/W.L.It means if designer is restriced to some large area (say for a capacitor) for which random mismatch value is minimum and beyond which gradient variability comes into picture, then by using common centroid approach this limitation value can be improved.Now he can take some more large area,.

The pelgrom model merely states that mismatch is inversely proportional to area, with some specific mismatch coefficient which is normally a characterized quantity dependent on process. It completely ignores systematic variations like die location or oxide gradient. So bringing in gradient or common centroid is out of the picture. And I emphasize that it is a "model".

The "systematic" aspect this equation brings in is more related to process. The mismatch coefficient is a characterized quantity on a statistically large enough sample, so it really doesnt say why the mismatch occurs, although many have come up with theories such as edge etching or overlap capacitance etc. But it's useful, because it's characterized, and represents the mismatch seen in actual silicon populations, so is probably a better "guess" on the true mismatch your designs will see.

Regarding systematic mismatch-For mismatch charcaterization of capacitors, parallel combination of unit capacitors has been taken.These provides a constant area/periphery ratio and avoid process induced systematic errors. how?

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the gradients present is small and medium sized dies can be approximated by planes..i dont understand this statement. I thought wafer has only 2 planes.vertical and horizontal.'n' number of planes.how?

An analysis of mismatch in multi-unit cap can be found in:
J.-B. Shyu, G. C. Temes, and K. Yao, “Random errors in MOS capacitors,” IEEE J. Solid-State Circuits, vol. 17, no. 6, pp. 1070-1076, Dec. 1982.