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[SOLVED] FFT core - Xilinx ise - This file cannot be synthesized

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medra

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FFT core - Xilinx ise

Hi all

after generating the FFT core in xilinx ise , I found that comment on top of the file:

" This file cannot be synthesized and should only be used with supported simulation tools."

what does that means??
 

Hi medra,
It could be due to the reason that the kind of simulator you are using for the synthesis of the file is not compatible for it.
 

Are you looking at the Verilog/HDL file that CoreGen produced? If so then that is not the core itself but a behavioural model for simulation only.
 
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    medra

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Rob B said:
Are you looking at the Verilog/HDL file that CoreGen produced? If so then that is not the core itself but a behavioural model for simulation only.
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Thanks Rob B , you must be right , the core already worked with me on the kit so this file must be for simulations only.
 

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