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How does drive strength effect delay?

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Zephr

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Hi ALL

Wanted to know what happens to the delay if i use an inverter with drive strength of 1X (capacitive load "C") v/s an inverter of strength 4X (same load capacitance "C").

I think that the delay will reduce? Is it due to the W/L ratio. Please comment.

Also how do you detect address fault lines in RAM. Suppose two decoder lines are swapped, how to detect those. Does it effect the functionality of the RAM (in case of single port). you are reading and writing to the same faulty address?

Thanks
 

My suggestion is to study logical effort.

As for the 2nd question, you won't be able to find if word lines are swapped since the function of the RAM is still the same and the RAM works without any issue.
 

Yes there will be reduction in delay... because current is increased by 4 times, the capacitor charging time will reduce by four times.
and thus the delay.
Well, about the address swapping, the ram will work properly, as you said writing & reading from same swapped locations.
We can say that, its your custom design for decoder. Only the thing is, physical location of the RAM cell will be different in this case as compared to conventional RAM.
 
When you increase the transistor size, you also increase the input capacitance, which contributes the slower switching(assuming the same driver). Basically switching get slower, but charging/discharging the output load gets faster. It's a trade off and you won't be able to find the answer without proper analysis of a whole picture.

Again, study Logical Effort. EDA tools are now using this model to optimize the timing.
 
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    Zephr

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Rightly said. When you start increasing, delay will only get decreased upto a certain extent and after that it will start increasing as the input cap also increases with increasing the size of the transistors.

There is a good book by Ivans Sutherland which talks of this and much more. Go through it.

best regards
 

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