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via affect entire board ??

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kabaleevisu

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Hi everyone,

i designed xilinx usb jtag board, in this board nearly 120 via is present in the board if via affect design.i think this board should route in more than 2 layer ( in my design 3.3V ,1.8V,5V are used i think 4 layer is possible i doesnot know correct factor ) but in my client ask to design in 2layer i have dough via affect entire board

NOTE:

what are factor need to design high speed board (like 4 laye and 6 layer etc )to choose correct stackup

is it related to VCC and board size


because still now i am design 2 layer board only please any one help me to learn high speed design
 

if you want to design high speed board consist of FPGA and all,,,you need multi layer card...there you can make all power section as split plane, and ground plane .. batter option always is after the top and and bottom layer use ground plane after this layer you can use other layer as signal layer..i think via is not a problem it depends on number of nets...

Regards
Praveen

---------- Post added at 18:14 ---------- Previous post was at 18:13 ----------

and please conform the board size..
 
hi praveen
thanks.In my design power trace and ground trace are near . is it affect any thing
and 5v and 3.3Vtrace are very close . is it create any problem
 

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Hi kapil as per your image 10 mil air gap is sufficient.. but i dont why you give more trace width for 3.3v and less for 5v if the current is less then 1amp you can go ahead with your design..but i dont think there is a high current.

Regards
Pravee
 

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ya i agree with praveenlb. why did you do that?
 

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