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Cadence RTLCompiler, how to prevent re-synthesis of the same module

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zhipeng

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Say, in the top level verilog netlist, it instantiates four instances of the same module DECODER.

After RTLCompiler has done elaborate and synthesis, they becomes instances of four differently-named modules, DECODER, DECODER_1667, DECODER_1668, and DECODER_1669.

How do I prevent the same module been renamed and re-synthesized to different implementations?

Later in hierarchical P&R, if I make one of the four copies as master partition, what is the command to make the other three into clones of the master partition?
 

the tools need to rename the same module instantiate multi time, this phase is call uniquify, because each modules will have their own timing constraints...
Using a unique module is only interesting to develop & maintain only one code versus x, for backedn tool, each logic will have his own attributs...
 
Hi zhi,
Default RTLcompiler uniquify the design during Global mapping. This will improve the QoR . If you dont want to uniquify and OK on QoR effect.
You can use set_attr minimize_uniquify true [find / -subdesign DECODER] or full design set_attr minimize_uniquify true / ..

Note: this command works in latest RC10.1 release only.
 
Thank you very much, aravind!

If the four encoders are uniquified, later in hierarchical P&R, is there a way to make the other three into clones of the master partition?
what is the command to make the hierarchical cell into a clone partition of a master partition? I could not find the relevant lines in soceUG.pdf...
 

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