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Synopsys DFT 2008.9 DFT insert_dft

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charles_hoho

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Hi friends,

I got error when I run DFT 2008.9. The command "insert_dft" responds "Invalid test protocol". The old command "inser_scan" is supported.
Run "set_dft_signal" responds "-type not found". What type should I set?
As I know, the Test_Compiler "set_scan_signal" type is "test_scan_enable".
Why it is wrond on DFT_COmpiler?:-:)-(
 

Hi,

There is some information you need to provide to the tool before you can insert scan.

Did you setup: scan enable, scan clock, scan style, ...

Try dft_drc -verbose

I would not move on until all warnings and errors are fixed.
 

Hi Sir,

I have done Signal Declaration as below:
---------------------------------------------
set_dft_signal -view spec -type TestMode -port prog0 -active_state 1
set_dft_signal -view spec -type Reset -port reset_n -active_state 0
set_dft_signal -view spec -type ScanClock -port clk_i
set_dft_signal -view spec -type ScanEnable -port prog1 -active_state 1
set_dft_signal -view spec -type ScanDataIn -port prog3
set_dft_signal -view spec -type ScanDataOut -port clk_o
----------------------------------------------
The Warnings are
Warning: Clock input CK of DFF clock_gen_u/counter_reg[8] was not controlled. (D1-3)
Warning: Clock input CK of DFF clock_gen_u/counter_reg[6] was not controlled. (D1-4)
Warning: Clock input CK of DFF clock_gen_u/counter_reg[5] was not controlled. (D1-5)
...
...
...
----------------------------------------------
The Netlists are
SDFFRHQX1 \counter_reg[8] ( .D(N14), .SI(1'b0), .SE(1'b0), .CK(clk), .RN(
rst_n), .Q(\counter[8] ) );
SDFFRHQX1 \counter_reg[6] ( .D(N12), .SI(1'b0), .SE(1'b0), .CK(clk), .RN(
rst_n), .Q(cnt[6]) );
----------------------------------------------
Do you think the Scan_Enable is not correctly setup?

I am sure that
set_dft_signal -view spec -type ScanEnable -port prog1 -active_state 1
=> Accepted dft signal specification for modes: all_dft

Do you have any golden script of DFT, just basic function?

Thanks.
 

Trace the clk connected to counter_reg*. I suspect the clock is generated by some internal logic and not externally controllable. however, the original error regarding test protocol is something else, but clean the issues one by one.
 

Hi, you define scan clock to be clk_i. Does clk_i drive the clock pins of your flops directly? Or is there some gating function that enables clk?
 

jpvSoccer said:
Hi, you define scan clock to be clk_i. Does clk_i drive the clock pins of your flops directly? Or is there some gating function that enables clk?
Click to expand...

Hi,

I this RTL verilog is very simple as below,
module count(
counter,
rst_n,
clk
);
input clk;
input rst_n;

output [7:0] counter;
reg [7:0] counter;

always @(posedge clk or negedge rst_n)
if (!rst_n)
counter <= 0;
else
counter <= counter + 1;

endmodule

----------------------------------------------
DFT script,
read_file -f verilog ./src/count.v
current_design count
link
check_design

create_clock -period 80 -waveform [list 0 40] -name clk clk
set_input_delay 2.0 -clock clk [all_inputs]
set test_default_scan_style multiplexed_flip_flop

create_port -dir in scan_mode
create_port -dir in scan_en
create_port -dir in scan_clk
create_port -dir in scan_in
create_port -dir in scan_rst
create_port -dir out scan_out

compile -scan

set_dft_signal -view spec -type TestMode -port scan_mode -active_state 1
set_dft_signal -view spec -type Reset -port scan_rst -active_state 0
set_dft_signal -view spec -type ScanClock -port scan_clk
set_dft_signal -view spec -type ScanEnable -port scan_en -active_state 1
set_dft_signal -view spec -type ScanDataIn -port scan_in
set_dft_signal -view spec -type ScanDataOut -port scan_out

create_test_protocol
dft_drc -verbose
write -format verilog -hierarchy -output count_scan.v
set_dft_configuration -scan enable
set_dft_configuration -fix_set enable
set_dft_configuration -fix_clock enable
set_dft_configuration -fix_bus enable
set_dft_configuration -fix_bidirectional enable
set_dft_configuration -control_points enable

insert_dft
--------------------------------------------------------
DRC Warings,
-----------------------------------------------------------------
Begin Pre-DFT violations...

Warning: Clock input CK of DFF counter_reg[7] was not controlled. (D1-1)
Warning: Clock input CK of DFF counter_reg[2] was not controlled. (D1-2)
Warning: Clock input CK of DFF counter_reg[3] was not controlled. (D1-3)
Warning: Clock input CK of DFF counter_reg[4] was not controlled. (D1-4)
Warning: Clock input CK of DFF counter_reg[5] was not controlled. (D1-5)
Warning: Clock input CK of DFF counter_reg[6] was not controlled. (D1-6)
Warning: Clock input CK of DFF counter_reg[1] was not controlled. (D1-7)
Warning: Clock input CK of DFF counter_reg[0] was not controlled. (D1-8)
Warning: Reset input RN of DFF counter_reg[7] was not controlled. (D3-1)
Warning: Reset input RN of DFF counter_reg[2] was not controlled. (D3-2)
Warning: Reset input RN of DFF counter_reg[3] was not controlled. (D3-3)
Warning: Reset input RN of DFF counter_reg[4] was not controlled. (D3-4)
Warning: Reset input RN of DFF counter_reg[5] was not controlled. (D3-5)
Warning: Reset input RN of DFF counter_reg[6] was not controlled. (D3-6)
Warning: Reset input RN of DFF counter_reg[1] was not controlled. (D3-7)
Warning: Reset input RN of DFF counter_reg[0] was not controlled. (D3-8)
--------------------------------------------------------------------------
insert_dft message,
Information: Starting test design rule checking. (TEST-222)
Warning: Violations occurred during test design rule checking. (TEST-124)
Information: Test design rule checking completed. (TEST-123)
Running Autofix
Architecting Test Points

Information: Starting test design rule checking. (TEST-222)
Warning: Violations occurred during test design rule checking. (TEST-124)
Information: Test design rule checking completed. (TEST-123)
* "/data/soc1/testc/test/bd3202/rtl/syn/mask/count_CONTROL_FORCE.v" file correctly generated *
Loading verilog file '/data/soc1/testc/test/bd3202/rtl/syn/mask/count_CONTROL_FORCE.v'
Detecting input file type automatically (-rtl or -netlist).
Running DC verilog reader
Reading with Presto HDL Compiler (equivalent to -rtl option).
Running PRESTO HDLC
Compiling source file /data/soc1/testc/test/bd3202/rtl/syn/mask/count_CONTROL_FORCE.v
Presto compilation completed successfully.
Removing netlist file '/data/soc1/testc/test/bd3202/rtl/syn/mask/count_CONTROL_FORCE.v'...
Structuring 'count_CONTROL_FORCE'
Mapping 'count_CONTROL_FORCE'
Warning: Clock information for all sequential cells of design is missing. (TEST-374)
Architecting Scan Chains
Mapping New Logic
Information: Scan insertion did not build any scan chains. (TEST-176)
Information: Scan routing is not complete. Signals 'serial or scan_enables' need to be routed. (TEST-899)
Information: DFT insertion was not successful. There were unrecoverable processing errors. (TEST-211)
 

charles_hoho said:
Hi,

I this RTL verilog is very simple as below,
module count(
counter,
rst_n,
clk
);
input clk;
input rst_n;

output [7:0] counter;
reg [7:0] counter;

always @(posedge clk or negedge rst_n)
if (!rst_n)
counter <= 0;
else
counter <= counter + 1;

endmodule

----------------------------------------------
DFT script,
read_file -f verilog ./src/count.v
current_design count
link
check_design

create_clock -period 80 -waveform [list 0 40] -name clk clk
set_input_delay 2.0 -clock clk [all_inputs]
set test_default_scan_style multiplexed_flip_flop

create_port -dir in scan_mode
create_port -dir in scan_en
create_port -dir in scan_clk
create_port -dir in scan_in
create_port -dir in scan_rst
create_port -dir out scan_out

compile -scan

set_dft_signal -view spec -type TestMode -port scan_mode -active_state 1
set_dft_signal -view spec -type Reset -port scan_rst -active_state 0
set_dft_signal -view spec -type ScanClock -port scan_clk
set_dft_signal -view spec -type ScanEnable -port scan_en -active_state 1
set_dft_signal -view spec -type ScanDataIn -port scan_in
set_dft_signal -view spec -type ScanDataOut -port scan_out

create_test_protocol
dft_drc -verbose
write -format verilog -hierarchy -output count_scan.v
set_dft_configuration -scan enable
set_dft_configuration -fix_set enable
set_dft_configuration -fix_clock enable
set_dft_configuration -fix_bus enable
set_dft_configuration -fix_bidirectional enable
set_dft_configuration -control_points enable

insert_dft
--------------------------------------------------------
DRC Warings,
-----------------------------------------------------------------
Begin Pre-DFT violations...

Warning: Clock input CK of DFF counter_reg[7] was not controlled. (D1-1)
Warning: Clock input CK of DFF counter_reg[2] was not controlled. (D1-2)
Warning: Clock input CK of DFF counter_reg[3] was not controlled. (D1-3)
Warning: Clock input CK of DFF counter_reg[4] was not controlled. (D1-4)
Warning: Clock input CK of DFF counter_reg[5] was not controlled. (D1-5)
Warning: Clock input CK of DFF counter_reg[6] was not controlled. (D1-6)
Warning: Clock input CK of DFF counter_reg[1] was not controlled. (D1-7)
Warning: Clock input CK of DFF counter_reg[0] was not controlled. (D1-8)
Warning: Reset input RN of DFF counter_reg[7] was not controlled. (D3-1)
Warning: Reset input RN of DFF counter_reg[2] was not controlled. (D3-2)
Warning: Reset input RN of DFF counter_reg[3] was not controlled. (D3-3)
Warning: Reset input RN of DFF counter_reg[4] was not controlled. (D3-4)
Warning: Reset input RN of DFF counter_reg[5] was not controlled. (D3-5)
Warning: Reset input RN of DFF counter_reg[6] was not controlled. (D3-6)
Warning: Reset input RN of DFF counter_reg[1] was not controlled. (D3-7)
Warning: Reset input RN of DFF counter_reg[0] was not controlled. (D3-8)
--------------------------------------------------------------------------
insert_dft message,
Information: Starting test design rule checking. (TEST-222)
Warning: Violations occurred during test design rule checking. (TEST-124)
Information: Test design rule checking completed. (TEST-123)
Running Autofix
Architecting Test Points

Information: Starting test design rule checking. (TEST-222)
Warning: Violations occurred during test design rule checking. (TEST-124)
Information: Test design rule checking completed. (TEST-123)
* "/data/soc1/testc/test/bd3202/rtl/syn/mask/count_CONTROL_FORCE.v" file correctly generated *
Loading verilog file '/data/soc1/testc/test/bd3202/rtl/syn/mask/count_CONTROL_FORCE.v'
Detecting input file type automatically (-rtl or -netlist).
Running DC verilog reader
Reading with Presto HDL Compiler (equivalent to -rtl option).
Running PRESTO HDLC
Compiling source file /data/soc1/testc/test/bd3202/rtl/syn/mask/count_CONTROL_FORCE.v
Presto compilation completed successfully.
Removing netlist file '/data/soc1/testc/test/bd3202/rtl/syn/mask/count_CONTROL_FORCE.v'...
Structuring 'count_CONTROL_FORCE'
Mapping 'count_CONTROL_FORCE'
Warning: Clock information for all sequential cells of design is missing. (TEST-374)
Architecting Scan Chains
Mapping New Logic
Information: Scan insertion did not build any scan chains. (TEST-176)
Information: Scan routing is not complete. Signals 'serial or scan_enables' need to be routed. (TEST-899)
Information: DFT insertion was not successful. There were unrecoverable processing errors. (TEST-211)
Click to expand...


In scan mode , clock is not controllering the registers, you can give the clk as a scanclock signal , below is one of the way:
read_file -f verilog rtl.v
current_design count
check_design
link

create_clock -period 80 -name clk -waveform {0 40} clk
set_input_delay 2.0 -clock clk [all_inputs]

create_port -dir in scan_en
create_port -dir in scan_in
create_port -dir out scan_out

set_dft_signal -view existing_dft -type Reset -port rst_n -active_state 0
set_dft_signal -view existing_dft -type ScanClock -port clk -timing {45 55}
set_dft_signal -view spec -type ScanEnable -port scan_en -active_state 1
set_dft_signal -view spec -type ScanDataIn -port scan_in
set_dft_signal -view spec -type ScanDataOut -port scan_out
compile -scan

create_test_protocol
dft_drc -v
insert_dft

Hope , it will work.
 
Hi, to add to the above comment...
In general:
1) your main clock is set to be scan clock
2) if you cannot control your resets/clocks externally you need a testMode signal that is used to mux primary inputs around the internally generated ones; these signal and mux functions are in your RTL.
3) for real designs we want to share input/outputs with scan data inputs and scan data ouputs
4) run the drc rule checker before you compile your design to gates

For your design: try this before you compile -scan
read_file -f verilog ./src/count.v
current_design count
link
check_design
create_clock -period 80 -waveform[list 0 40] -name clk clk
set_input_delay 2.0 -clock clk [all_inputs]
set test_default_scan_style multiplexed_flip_flop
create_test_protocol -infer_async -infer_clock
dft_drc -verbose

If you are "dft" clean at this point, then go ahead and compile to gates.


Note1: you typically don't need to create ports; the tool will do that for you
 
dianin said:
In scan mode , clock is not controllering the registers, you can give the clk as a scanclock signal , below is one of the way:
read_file -f verilog rtl.v
current_design count
check_design
link

create_clock -period 80 -name clk -waveform {0 40} clk
set_input_delay 2.0 -clock clk [all_inputs]

create_port -dir in scan_en
create_port -dir in scan_in
create_port -dir out scan_out

set_dft_signal -view existing_dft -type Reset -port rst_n -active_state 0
set_dft_signal -view existing_dft -type ScanClock -port clk -timing {45 55}
set_dft_signal -view spec -type ScanEnable -port scan_en -active_state 1
set_dft_signal -view spec -type ScanDataIn -port scan_in
set_dft_signal -view spec -type ScanDataOut -port scan_out
compile -scan

create_test_protocol
dft_drc -v
insert_dft

Hope , it will work.
Click to expand...

Hi,

Thanks a lot!!!!!!!!
It really works.
so it is the problem that I set the wrong option to ths scan clock.
I must set "existing" option to set_dft_signal to clock.

:razz:
 

Not only set "existing" option to set_dft_signal when define scanclock, but you have to specify the port which the clock comes from(set_dft_signal -view existing_dft -type ScanClock -port clk -timing {45 55}).
 

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