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setup and hold time (interview question)

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gold_kiss

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setup and hold time calculation

Hi,

Consider a system which works at a clock frequency of 100Mhz. Suppose you have a setup voilation of 0.2ns and hold voilation of 0.8ns calculate the clock frequency at which the system work fine?

Hey guys, pls give me equations for tsetup and thold...also along with your answers.

Cheers,
Gold_kiss
 

how to hold an interview

There is no equation for setup and hold time; it is a definition. Setup is the time the data signal must be valid at a flip-flop or latch input before the clock transition. Hold time is the time the data signal must remain valid after the clock transition. Let's see: a 100MHz signal has a 10ns period. If it needs 0.8ns more setup time to remove the setup violation and 0.2ns more hold time to remove the hold time violation, the minimum clock period that will work is 10ns+0.8ns+0.2ns or 11ns. This gives a max clock frequency of 1/11ns or 90.9MHz.
 

setup time equation

again, you are so....so....so....so....
lucky for having these kind of Q's in an Interview.
 
setup time hold time definition

For calculation of the minimum clock frequency it is necessary to know also a propagation delay previous cascade, a delay in a transmission line and skew different clock.
 

setup time formula

Just make sure that once you have added hold time, setup time and propagation delay, the clock period has not been exceeded.

t_clock < t_setup + t_hold + t_prop_delay

Another way of looking at it is that the time left for your logic operation between the two registers equals to the clock period minus the setup and hold time.

p.s. Hawk, you said it was easy but never gave a solution...:)
 
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setup hold time violation

I copied an example about how to calculate setup and hold time from a book(in the attachment).
giggs11,I think the formula u gave us is wrong, according to the waveform
in the example, I get this:
T_setup ＝（T_clock ＋ △T）－T_combin_logic，T_hold=_combin_logic－△T
In above interview quiz ,△T=0. So,the equation is:
T_setup ＝（T_clock ＋ △T）－
T_combin_logic<=T_clock-T_setup =10ns-0.2ns=9.8ns
This gives a max clock frequency of 1/9.8ns.
 

signal integrity interview question

gold_kiss said:
Hi,

Consider a system which works at a clock frequency of 100Mhz. Suppose you have a setup voilation of 0.2ns and hold voilation of 0.8ns calculate the clock frequency at which the system work fine?

Hey guys, pls give me equations for tsetup and thold...also along with your answers.

Cheers,
Gold_kiss
Click to expand...

For setup time,it's easy. The system can have a period about (10ns+0.2ns)=10.2ns, which means 98MHz. But for hold time violation 0.8ns, I am rather confused. Slow down the system clock has no effect on hold time since hold time compares the same clock edge. The only method to solve hold violation is adding buffers, not slow down the whole system clock.
Am I right..................?
 
set up time and hold time calculation

Who can upload some doc about timing path analyzer in IC design?
 

setup time calculation

For setup time,it's easy. The system can have a period about (10ns+0.2ns)=10.2ns, which means 98MHz. But for hold time violation 0.8ns, I am rather confused. Slow down the system clock has no effect on hold time since hold time compares the same clock edge. The only method to solve hold violation is adding buffers, not slow down the whole system clock.
Am I right..................?

------------------------------------------------------------------------------------
i think your analysis is right.

--always@samrt
 

setup and hold time forumla frequency

eexuke said:
... The only method to solve hold violation is adding buffers, not slow down the whole system clock.
Am I right..................?
Click to expand...

In multiphase clock source for reception You can use shift clock phase, or use delay line.
 

how maximum frequency depends on setup time?

I heard that the hold time does not depend on the frequency of operation. Is this right. If so, how could we overcome the hold time violation?
 

clock frequency set up and hold

reddy said:
I heard that the hold time does not depend on the frequency of operation. Is this right. If so, how could we overcome the hold time violation?
Click to expand...

For certain reason, hold time of cell decided by the cell lib. ^_^

Now some synthesis tools can do fix the hold time, such as BG, DC.
You can get the detail command from the GU of those tools.

Good Luck
 

setup and hold min and max violations

Try this answer,

Setup time is the time your girlfriend is willing to wait for you,
and Holdtime is the time you are willing to wait for your girlfrirnd.

:p
 

setup and hold + frequency

so what was the final answer to the question by gold_kiss? What duncan is saying, fits giggs11's formula (if we take propogation delay=0, as it's not given).

But what abt eexuke's claim that the hold_time won't play any role in finding the correct max clk frequency the system can handle with the ts & th constraints?

samc, could u explain the uploaded diagram further, like how the signals are behaving exactly? which book u took this diagram from?

could someone help me to find some good material (preferably online), which can help me get my concepts cleared about the flipflops' & latchs' timing behaviour, timing calculations, propogation delay, max/min frequency calculations in a circuit.? would be useful if it is in problem-answer form, useful for interviews also.

thanx a lot.
 

interview questions set up hold time

This is a trick question.

If you slow down the clock frequency, you can fix the setup violation.

However, you cannot fix the hold time violation by slowing down the clock. You need to add buffers to path to make sure it transistions later and is captured by the next rising edge.

Therefore, the answer is the system will not work until you fix the hold time vioation. Then, you run the clock at the speed mentioned above.

Another interview question is this: If you only have 1 chance to fix a setup or hold time violation, which do you choose?

Answer is fix the hold time violation, because the setup violation can always be fixed by just slowing down the clock.
 
setup and hold time violation + pdf

Setup is the time the data signal must be valid before the clock transition. Hold time is the time the data signal must remain valid after the clock transition.Setup time and hold time is always larger than hte settle time of sample circuits,and so on.
 

set up time +clock +settle

I think the answer is :

because we have 0.2ns setup violation, so if clock cycle

is 10.2 ns, then setup violtion is eliminated. for hold time

violation, we can add some delay in fastest path to eliminate

them.

so max operating is

1/ 10.2 ns.


best regards




gold_kiss said:
Hi,

Consider a system which works at a clock frequency of 100Mhz. Suppose you have a setup voilation of 0.2ns and hold voilation of 0.8ns calculate the clock frequency at which the system work fine?

Hey guys, pls give me equations for tsetup and thold...also along with your answers.

Cheers,
Gold_kiss
Click to expand...
 

clock setup and hold analysis

Hi,

We can overcome the set-up time, as discussed by other friends, by slowing down the Clock (10.2ns).

There is no way the existing Hardware work by changing the clock frequency!!! The only way to add additional hardware to the existing. If you do not want the hardware to change at all, then there is no way that the system will work at any frequency.

We can not overcome the Hold time violation, unless you change the existing system by adding addional delay interms of multiple gates or buffers.

Hope this would conclude ...!!!
 

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