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design of high speed transimpedence amplifier (texas instrument chip)

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sleepinglion

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Minimum trans-impedance bandwidth: 1 MHz
Bias current: 50pA
Gain Bandwidth: 90MHz
Maximum offset voltage: 25mV
Maximum input referred noise: 70nV/√Hz
CMRR: 110dB
Slew Rate: 80V/ms

can u give some suggestions how to design it or atleast how to proceed,
what kind of opamp topology should i use to have bias current of 50pA,with out too much increase in length,i am using tsmc-180n technology
 

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