altering the cone logic to increase the coverage in scan DFT

Hi.

I am new to scan DFT.

I attended an interview last week. They asked me to tell the different methods to increase the coverage. I ended up by saying some answers, but they asked me about the alteration of input or output cone logic to increase the coverage.
I never heard about that. Can some please explain how the alteration of cone logic will result in increase of coverage.

Hi, I guess they were trying to get at how to improve controllability and observability

The terms controllability and observability are measures of how testable a circuit is.

Logic cones are composed of the combinatorial logic that drive flop inputs.

Flops also drive these cones via their outputs.

The job of a scan-based DFT tool is to figure out how to sensitize the cones so that stuck-at faults can be detected and subsequently shifted out via the scan chain shift sequence.

An important aspect of DFT is the ability to control inputs to combinatorial clouds so that we can observe the results of the input changes on the output of the cloud. The shift in sequence sensitizes the cones of logic. The capture cycle samples the results of the sensitization. The shift cycle is used to observe the results of the sensitization.

A very complex block of combinatorial logic may be difficult to control all points so that a particular stuck-at 1 or 0 fault can be detected.

If we split the logic up in to less complex clouds (maybe by adding another register state), the controllability and observability will likely be improved. As such, the DFT tool may be able to generate a higher coverage test vector for the logic.