hamzah.aaaa
Newbie level 5
Dear All,
I am designing a digital small chip using Mentor Graphic IC Station tools.
I have finished all steps but I have LVS ERROR in the final. which states as:
Error: Different numbers of ports (see below).
Error: Power net missing in layout. Ground net missing in layout.
Although I have NOT these errors when I made the LVS check for the die before adding IO Pads.
The LVS report for the Die with and without PADs are attached.
I am designing a digital small chip using Mentor Graphic IC Station tools.
I have finished all steps but I have LVS ERROR in the final. which states as:
Error: Different numbers of ports (see below).
Error: Power net missing in layout. Ground net missing in layout.
Although I have NOT these errors when I made the LVS check for the die before adding IO Pads.
The LVS report for the Die with and without PADs are attached.