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[SOLVED] Compiling Schematic / VHDL to IC/VLSI Layout

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nbprashanth

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Hi guys. I just started learning VLSI and I was wondering if there is any software out there (or a set of tools) to convert a VHDL or Verilog code or Schematic Design into IC layout?

If not.... how are IC's designed? I am sure it is not possible for designers to draw transistor by transistor.... right?

I tried using Alliance tools in linux but found it to be a bit annoying due to the lack of proper tutorials. I would prefer windows tools if possible, but i am ok with linux also.

Thanks
 

Yes there are tools that can give you the IC layout from the VHDL/Verilog description. Usually you need a synthesis tool to obtain some gate-level netlist from the HDL description and then a Place and Route tool to produce the final layout. The tools perform all sorts of necessary optimizations (buffer insertion to satisfy timing constraints, synthesis of clock trees, routing to minimize coupling and crosstalk etc.). The Cadence tools for these functions are RTL Compiler for the synthesis step and SOC Encounter for the Place and Route step. There are similar tools from Mentor and Synopsis though.
 
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Thanks for answering.....
Can you mention the tools from Mentor and Synopsis? Are there any opensource/freeware tools? (Student edition or anything)
And can tanner tools do this?
 

for analog design you realy need to do the layout for each transistor as they do not have same size. for digital you can make all the devices in a row having same height, but different width.
hence you can use system based auto routing.

one good free tool for this is MAGIC layout tool.

give it a try.

all the commercial tools do not have any student version. they do have educational programs but for this your university / college should purchase the subsidized tools.

hock
 

I will give magic and electric a try.
Thanks a lot for helping me guys!
 

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