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startup ciruit ...how does the node 1 go to vdd...?Thankyou...

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bhanu.somisetty

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Hi All...

In the attachment,the startup circuit is used to avoid a condition "where the gate voltages of transistor M1,M2 become zero and M3,M4 become VDD and the circuit doesnt work".
Can anyone explain,why the gate voltages of M1,M2 go to zero and M3,M4 go to VDD?

Thanks a lot....
 

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If you ignore the startup circuit the circuit is 'bistable'. It has two stable states - working as designed and with all transistors 'off'. When you power up the circuit the gates of M1 and M2 could be VSS and the gates of M3 and M4 could be VDD and the circuit would happily stay like that. The startup circuit stops that from happening without affecting the normal operation.

Keith
 

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Hi

Thanks for the explanation.Would you pls let me "why the M3 and M4 gate voltage goes to VDD?"
 

This device is diode connected. At startup with zero current flowing the vgs will stay below vth (it does not need to be at vdd) when the power is applied slowly.
 
The PMOS transistors have the bulk connected to VDD. The gate capacitance will tend to keep the transistors turned off although the drain capacitance and leakage of the NMOS will try to pull the PMOS gates low. The end result is unpredictable without a startup circuit.

Keith
 
if no start up circuit, when the circuit is initial, M1/M2 and M3/M4 are depth linear， So gate voltage of M1 and M2 is about gnd, gate voltage of M3 and M4 is vdd,
 

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