Let's disscuss the sign-off STA corner problems

Hi,

Let's disscuss the following questions.

1.What's the difference between the following SPEF
cbest cworst rcbest rcworst typical

2.What do BC WC WCL ML stand for?

3.Why we do sign-off STA with the following method
BC+cbest/WC+rcworst/ML+rcbest for hold time check
WC+rcworst/WCL+rcworst for setup time check

Thanks.
Best Regards,
Ritchie

Hi,

1.

C stands for capacitance and r stands for resistance (In general). So best generally takes optimum values (To account for small delay Numbers). And Worst takes pessimistic values (Large delays). So we can have the following variations
1. Worst Cap Worst Resistance
2. Best Cap Best Resistance
3. Worst cap Best Resistance
4. Best Cap and worst resistance

I haven't seen best case and worst case spef. I think SPEF is corner independent. Can someone throw light ?

Based on the availability of .libs, we can do Timing Analysis in all possible combinations and find out whether timing is met or not.

2.
BC Best Case
WC Worst Case
WCL Worst Case Low Temperature (To account for NBTI ? Or Inductance ?) I dont know what L stands)
ML I haven't heard this (But may be with Inductance into consideration)

3.Why we do sign-off STA with the following method
BC+cbest/WC+rcworst/ML+rcbest for hold time check
WC+rcworst/WCL+rcworst for setup time check

We consider pessimistic approach in general. I mean , for how much ever worse a parameter gets, we should still be able to close timing. Setup check pessimism analysis goes as follows
For worst delay possible(slowest possible delay) with data path and for best delay possible with clock path, the data should still be captured by the clock well before setup time requirements.

And for hold, for best possible (fastest data path delays) and for max skew possible with clock, the data should still not change untill hold time is passed.

Regards,
R.Srideepa

Hi Srideepa,

Thanks for your reply. Then the first question is done.

For the second question, WCL,ML may be related to low power design but I am still not sure. I hope someone can answer.

For the third question, we have a project that use BC+cbest/WC+rcworst/ML+rcbest corner for hold time check and WC+rcworst/WCL+rcworst for setup check, and max negative slack will happen in each of the corner. That is to say, we can not tell which corner is the worst and which corner is the best situation for hold time or setup time check.
I hope someone can detailed explained these corner combination.

Thanks
BR Ritchie

snoopy821215 said:

For the second question, WCL,ML may be related to low power design but I am still not sure. I hope someone can answer.

Click to expand...

STA is just an analysis of timing and has nothing to do with low power design.

For the third question, we have a project that use BC+cbest/WC+rcworst/ML+rcbest corner for hold time check and WC+rcworst/WCL+rcworst for setup check, and max negative slack will happen in each of the corner. That is to say, we can not tell which corner is the worst and which corner is the best situation for hold time or setup time check.

Click to expand...

In your context, the worst corner and the best corner are refered to as slow corner and fast corner, respectively. Other way to look is the worst corner for setup check is slow corner, and the worst corner for hold check is fast corner. So, it really depends on how you use the term 'worst' and 'best'.