Setup and Hold check in Primetime ?

Dear all,
I have one question about the timing, please help me !!

We know the setup time check at worst case condition.
Is it possible the timing is met at worst-case condition, but
violate at best-case condition ? And why?

Thanks all and have a nice day. ^^

Yes - hold violations are more likely in best case as the logic is faster.

Thank. I should clarify my doubt again.

In the setup time check, we will calculate the :
1. Maximun delay for data path @worst case
2. Minimun delay for clk path @worst case
And suppose in this condition(@worst), we got the positive slack.

Is it possibile we could get negative slack in such condition when we calculate setup time?
1. Maximun delay for data path @best case
2. Minimun delay for clk path @best case

Thanks again. ^^

No if in your design there is no setup timing violation in worst case, then for best case also there will not be any setup violation.

Regards,
Shitansh Vaghela

Thanks for the reply.

Dear Shitansh,
Is there any proof or material can help me understand this case ?

agrey said:

Is there any proof or material can help me understand this case ?

Click to expand...

Think over it its basic concept you might get your answer.

In case you need some material then read this book Static Timing Analysis for Nanometer Designs A Practical Approach

You will get answers of all questions.

HTH
Shitansh Vaghela

I think it is a common mistake to assume that meeting setup time with slow corner can assure the setup time to meet with fast corner.
In the most case, it is true, but not always.

The most commonly seen example is the timing analysis on the interface signals.

Suppose you have both of clock and data comming from outside of the chip. CLock tree is very deep and data path is so so deep. In this scenario, running STA with slow corner will likely give you a greater slack than fast corner, because of the deep clock tree.

here is the example.
Assume the following timing spec.
Clock pin to CK pin of the most critical flop : 5ns(slow corner)
Data pin to D pin of the same flop : 4ns(slow corner)
clock cycle : 2ns

If the clock and data comes into the chip at the same time, they have 3ns slack(ignoring setup time of the flop).

Now let's say fast corner is twice as fast as slow corner. This makes clock path 2.5ns, and data path 2ns.. Well, this makes the setup slack 2.5ns, which is lesser slack than the slow corner. You see the picture.

I have seen this issue on every chips I worked on, though it was opposite case. i.e. hold timing is met with fast corner, but violates big time with slow corner. The opposite to this case, meeting setup with slow and violating it with fast, could happen in theory.

@lostinxlation
in ur example also setup violation (3 ns) is more in worst corner only NOT in best corner ..

what interests me more is scenerio asked by agrey, is it possible to violate setup at best case (fast corner) and vice versa (violate hold at worstcase, slow corner) ???

jaydip said:

@lostinxlation
in ur example also setup violation (3 ns) is more in worst corner only NOT in best corner ..

Click to expand...

3ns in my example is positive slack. Fast corner with 2.5ns positive slack is more critical than slow corner with 3ns positive slack, which shows fast corner can be more critical than slow corner in some scenario.

what interests me more is scenerio asked by agrey, is it possible to violate setup at best case (fast corner) and vice versa (violate hold at worstcase, slow corner) ???

Click to expand...

It usually doesn't happen on flop to flop paths, IF it is designed well. But if it's designed poorly, like some of the cells used on clock tree or data path exceeding the slew limit of timing arc and timing calculation going extrapolation, you never know what would happen.

oh !! got it .. thanks ..

would like to summarize this:
- if amount by which delay scales down from worst corner to fast corner is not same for data and clock paths, and if data path scales down lesser than clock path, we may see setup violation under best corner ... here is an example:

Worst corner:
clk path delay 6
data path delay 8
clk period 2

setup slack 0 (MET)

Best corner:
clk path delay 3 (clock delay scaled down by half)
data path delay 6 (data path delay scaled down marginally)
clk 2

set slack -1 (VIOLATION)

Similarly for hold.
- if amount by which delay scales up from best corner to worst corner is not same for data and clock paths, and if clock path scales up faster than data path, we may see hold violation under worst corner ... here is an example:

Best corner:
clk delay 5
data delay 6

Hold slack +1 (MET)

Worst corner:
clk delay 10 (clock path scaled up by half)
data delay 8 (data path scaled up marginally)

Hol slack -2 (VIOLATION)

Hi lostinxlation,
Is this correct ??

Jaydip

Yes, you are right.