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low power comparator design for SAR ADC

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eggzhang

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low power comparator

Can anyone suggest how to design a comparator for SAR ADC, aiming to achieve ultra-low power but with moderate speed?
 

low power nanowatt comparator

It seems I ask this question without first referring on the board. After searching, I read some paper from others' recommendation.

Latch comparator seems a better choice over conditional 2-stage amp. I plan to try two topologies, one is preamp with latch and the other is only dynamic latch comparator.

If I get the detailed SIM results later, I will post them here :)
 

low-power comparator

resolution?
 

designing a sar adc

resolution is moderate, 8 or 9 bits.
sample rate is also moderate, around 100KSPS.
Only tough requirement is power, aiming to achieving nanowatt level.
 

comparator design, low power

if you want to save power you should use dynamic comparator, but it can have really big offset ~100mV , and you will not be able to simulate all effects...
problem is that offset is usually not constant and directlly affects on adc performances...
comparator has to be much beter than 8 bits... if you want to achieve 8 bit adc resolution...
 
Hi, Pixel,

Can you explain why "offset is usually not constant"?

What is the assumption?

Thanks.
 
offset is a random variable. It's different from chip to chip, or die to die.
 
Hi

Is it good to use typical op-amp instead of comparator?

tnx
 

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