Annular rings at via: do they result in capacitive loading?

Hi All,
I am confused if removing annular rings at vias and at high-speed backplane connector pins helps in reducing capacitive loading and if yes then how, wont it effect the manufacturability and connection strength?
Also would like to know similar tricks in order to reduce capacitive loading of the signals?

Thanks and Regards,

Ricky

Ricky,
Imagine a via that has all anular rings intact through an 8 layer stackup. What you would end up with is 8 metal plates that will most certainly act as capacitors. In high speed design this is highly undesirable. Usually what is done to negate this is to remove unconnected pads on internal layers either in the PCB layout tool or in fabrication after gerbers are generated. I prefer to remove during the layout process. This gives me greater control over routing and plane generation. (unconnected pad removal capabilities vary between layout tools. You will want to research how your tool copes with pad removal or if it is even available)
One thing that will occure when removing pads is that inductance will increase somewhat. It is a good idea to model vias using some type of simulator to assure best results. Rf vias are the most critical and complex.

Backplanes are extremely critical in regards to vias and minimizing capacitance. Usually along with removing unused pads backplanes often require back-drilling to remove even more capacitance, and potential antennas.

I have never had an issue arise with manufacturability by removing unused pads on internal layers. This is a pretty standard process that you could discuss with your fabrication vendor.

Eda