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Altera MAXII FPGA problem concerning insufficient logic cells

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ZigaM

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Hello.

I have a problem with MAXII FPGA.

I want to save about 1500 values (16 bit).

I define array :
type int_array is array (0 to 1500) of STD_LOGIC_VECTOR (15 DOWNTO 0);

When I compile my project it ran out of logic cells. My device have only 1200 logic cells, while compiler needs 28000 cells :cry:

Does any one have any idea how can I realize my problem?


Thanx for replys.
 

Re: Altera MAXII problem

ZigaM said:
Hello.

I have a problem with MAXII FPGA.

I want to save about 1500 values (16 bit).

I define array :
type int_array is array (0 to 1500) of STD_LOGIC_VECTOR (15 DOWNTO 0);

When I compile my project it ran out of logic cells. My device have only 1200 logic cells, while compiler needs 28000 cells :cry:

Does any one have any idea how can I realize my problem?


Thanx for replys.
Click to expand...

if you want to restore 1500 values, I suggest you add a SRAM ,and let the CPLD control it.
 

    Z

    ZigaM

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Re: Altera MAXII problem

Yes, that can solve the problem, but I meant if there is another way without adding components. Only software solution?


Well, I will connect dsPIC to CPLD. Can I use PIC as memmory for CPLD?
 

Altera MAXII problem

A CPLD can not has so many Flip Flop to satisfy you requirement.
you can use FPGA ,but that will cost more.
If you use MCU to store data, make sure the ram space is enough, not only for data stack ,but also for the program.
 

    Z

    ZigaM

    Points: 2
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Re: Altera MAXII problem

Well, I already give up on program solution.

I am allready searching for parallel SRAM.
 

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