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Successive approximation register

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sar adc circuit projects

Can you guys post your SAR ADC circuit diagram here? i currently finished a 10MHz SAR ADC as a lab project, see anything i can help.
 

Re: SAR ADC

3x for the thesis
 

SAR ADC

hey me and my frndz designing sar adc and we ve designed s/h,dac,reg,opamp but no idea on sar.......pls someone help us..
 

Guys making a SAR logic is very simple.
A shift register with asynchronous reset will do the work you.

Refer to Dual Time Interleaved ADC paper by Ginsburg & Chandrakashan. I can't recall the year.

Added after 5 minutes:

Refer to this paper:
 
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Re: 8 bit sar adc schematic

Syukri said:
Hi all...

Generally speaking..al thing must be turn into netlist before it can be simulate but advancement in tools make it posible that the tools itself generate it for u.

Well in my SAR-ADC case...my partner can generate the netlist from verilog. there is some reason for this :

1. SAR and all ADC is considered as MIxed Signal System..coz there is an analogue part and digital part ( the SAR logic ). Analog Circuit need to done from scratch...either netlist or schematic entry...from circuit design to layout everything is manual, unless you have a library that has various type of device with various spec.

2. Simply becasue my analogue comparator, sample and hold and DAC is in netlist...so to integrate our part to become complete SAR-ADC everything must be in same format..in this case the netlist.

Added after 7 minutes:

As i always said..this is only for refference...copy on the design is prohibitted
Click to expand...



I am designing SAR adc i had design a DFF witha reset but by using this am not able to design a successive approximation logic and in some papers i had studied that DFF with set and reset pins are used for SAR logic can you please help me with this issues of designing..

thankyou

Regards,
Abhishek Mishra
 

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