What's the difference between these clocks??

(1) generated clock
(2) multiple clock
(3) ideal clock
(4) propagated clock

i am really confused by them, would you tell me what the difference is between them?
thanks a lot

Added after 4 minutes:

by the way, if i want to understand those concepts clearly, what should i learn? STA, CTS or other things? would you give me some advice?

What's the difference of these clocks??

(3) ideal
(4) with propagated delay.
i don't know how to express the difference between (1) and (2).

STA: static timing analyze. opposite to simulation. and it's based on paths without any input test vectors. I
CTS: clock tree synthesis. synthesis clock networks. It's very important in synthesis process. because it affects the timing information.

Re: What's the difference of these clocks??

Hi

For Multiple clock you can refer to below link. It means tghere are several clocks for Chip.

**broken link removed**

Regarding propagated clock, I guess Synopsys had a good paper, but couldnt find. Maybe below link can be a good starter.

**broken link removed**

Also below link has much information about clocks.

https://www.vlsichipdesign.com/


Cheers

Generated Clock

Hi,

A generated clock is a clock derived from a master clock. A master clock is a clock defined using the create_clock specification.

When a new clock is generated in a design that is based on a master clock, the new clock can be defined as a generated clock. For example, if there is a divide-by-3 circuitry for a clock, one would define a generated clock definition at the output of this circuitry. This definition is needed as STA does not know that the clock period has changed at the output of the divide-by logic, and more importantly what the new clock period is.


Above Figure shows an example of a generated clock which is a divide-by-2 of the master clock, CLKP.

create_clock -name CLKP 10 [get_pins UPLL0/CLKOUT]
# Create a master clock with name CLKP of period 10ns
# with 50% duty cycle at the CLKOUT pin of the PLL.

create_generated_clock -name CLKPDIV2 -source UPLL0/CLKOUT \
-divide_by 2 [get_pins UFF0/Q]
# Creates a generated clock with name CLKPDIV2 at the Q
# pin of flip-flop UFF0. The master clock is at the CLKOUT
# pin of PLL. And the period of the generated clock is double
# that of the clock CLKP, that is, 20ns.

HTH

Thanks all of you.

After reading your words and some paper, i have some idea about these clocks:

(1) generated clock:
it's generated by dividing or gating from the source clock, and it's defined by "create_generated_clock" in DC.

(2)multiple clock :
Maybe it's more appropriate if i call it multiple-cycle clock, which is related to multicycle paths. In DC/PT "set_multicycle_path" command makes timing check passed where combinational paths have more than one cycle delay.

(3)ideal clock:
It exists before CTS(pre layout). The clock network latency is set by estimating when we defined the clock.

(4)propagated clock:
It exists after layout. And "Set_propagated_clock" allows DC to calculate the actual clock latency of a clock tree (post layout).

Is that right?

Yes, You are right!.