A.N.
Newbie level 2
Hi everyone, I'm new to trying to hand-crank VHDL and I'm having a wee bit of a problem. I usually use auto-generated code so I'm not too used to writing it myself. The problem that I'm having is that the code is being generated with one-bit signals being defined as std_logic type but the application I'm using the code for requires all one-bit input/output signals to be in the form of std_logic_vector(0 DOWNTO 0).
For input signals, I've found that using A <= B(0); (where A is std_logic and B is std_logic_vector(0 DOWNTO 0)) works well. My problem is that I cannot find an equivalent for output signals, ie to go from std_logic to a std_logic_vector.
Any suggestions would be greatly appreciated.
Thanks,
Andy
For input signals, I've found that using A <= B(0); (where A is std_logic and B is std_logic_vector(0 DOWNTO 0)) works well. My problem is that I cannot find an equivalent for output signals, ie to go from std_logic to a std_logic_vector.
Any suggestions would be greatly appreciated.
Thanks,
Andy
