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why SR latch in PWM converter....?

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bharatsmile2007

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hi all,

what is the function of SR latch in PWM converter in DC-DC converters....?
any one tell me about the advantages of using SR-Latch?

Thanks a lot...
 

The question isn't particularly clear. If you refer to a SR latch between PWM comparator and output,
it's intended to prevent multiple pulses per PWM cycle, as clearly stated in most datasheets.
 
If you use a direct-coupled ramp comparator you will likely
see the output reswitch on H-L edges, as the ground is jacked
by the output switch current. Been there. You would not see
this in simulation until you include package parasitics.

In voltage mode control the set is the ramp-start and the
reset is the ramp:error amp comparison.

In current mode control the set is from the sync or clock, and
the reset is from the current sense.

In either case there may need to be a minimim "blanking"
time about the switch edges, or noise can still multi-switch the
output.
 
Usually, PMOS is set by CLK and reset by the output of PWM comparator. As you may know, CLK and the output of comparator is just like one shot pulse. So that you must use SR latch to latch logic level of PMOS gate.
 

Thanks everyone for the help...

can anyone tell me..if iam using PWM converter what should be the swing of the ramp signal to be used?
i mean how to decide the ramp swing?

Thanks
 

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