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How to do timing simulation in Modelsim

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Mkanimozhi

Mkanimozhi

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Hi Friends,

I need to do the timing simulation in modelsim, can any one tell me how to perform the timing simulation.

Thanks and Regards,
Kanimozhi.M
 

Timing Simulation

It is like doing normal simulation, just add the SDF file, search the manual for it and you will find the information.

The only trick is that you must compile your libraries properly. What is your platform? FPGA or ASIC?
 
Re: Timing Simulation

Hi ,
Thanks for your reply ,I Need to do in the ASIC and i don't know how to create the SDF file.

Regards,
Kanimozhi.M
 

Timing Simulation

It depends on the tools you use, you can do post synthesis timing simulation or post layout timing simulation. In the first case it will be your synthesis tool that will create the SDF file in the second case it is the technology mapper that creates the SDF file.
You have to look into the tools documentation because they are all different.
 
Timing Simulation

Hi ,
Am using the xilinx tool using that i generated the .SDF file,but i don't know the further procedure to do the timing simulation in modelsim,am using modelsim 6.3c.


Regards,
Kanimozhi.M
 

Re: Timing Simulation

If you just look into the manuals of modelsim, you will find the answer to your question:
Simulating VHDL Designs
A VHDL design is ready for simulation after it has been compiled with vcom and possibly optimized with vopt (see Optimizing Designs with vopt). The simulator may then be invoked with the name of the configuration or entity/architecture pair or the name you assigned to the optimized version of the design.

This example invokes vsim on the entity my_asic and the architecture structure:
vsim my_asic structure
vsim is capable of annotating a design using VITAL compliant models with timing data from an SDF file. You can specify the min:typ:max delay by invoking vsim with the -sdfmin, -sdftyp, or -sdfmax options. Using the SDF file f1.sdf in the current work directory, the following invocation of vsim annotates maximum timing values for the design unit my_asic:
vsim -sdfmax /my_asic=f1.sdf my_asic
By default, the timing checks within VITAL models are enabled. They can be disabled with the +notimingchecks option. For example:
vsim +notimingchecks topmod
If +notimingchecks is set on the vsim command line, the generic TimingChecksOn is set to FALSE for all VHDL Vital models with the Vital_level0 or Vital_level1 attribute. Setting this generic to FALSE disables the actual calls to the timing checks along with anything else that is present in the model's timing check block. In addition, if these models use the generic TimingChecksOn to control behavior beyond timing checks, this behavior will not occur. This can cause designs to simulate differently and provide different results.
By default, vopt does not fix the TimingChecksOn generic in Vital models. Instead, it lets the value float to allow for overriding at simulation time. If best performance and no timing checks are desired, +notimingchecks should be specified with vopt.
vopt +notimingchecks topmod
Specifying vopt +notimingchecks or -GTimingChecks=<FALSE/TRUE> will fix the generic value for simulation. As a consequence, using vsim +notimingchecks at simulation may not have any effect on the simulation depending on the optimization of the model.
Click to expand...
 

Re: Timing Simulation

you mean the Gate level simulation? you need the SDF and netlist ,better have no-timing check list!
 

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