Question about Icarus Verilog code syntax

genvar i;
generate
for(i=0;i<`ITERATIONS-1;i=i+1) begin:Loop
rotator U (clk,rst,x,y,z,x[i+1],y[i+1],z[i+1]);
defparam U.iteration = i;
defparam U.tangle = tanangle(i);
end
endgenerate

how i can change the above code by simple for loop without using generate loop....and how i can declare the 'i' other than genvar......because the above code is not supported by Icarus simulator....that's y

generate loop

Instantiate the block manually, it is pretty easy to do.

Re: generate loop

yes we can instantiate the block seperatly....but how we can instantiate the U.Iteration and U.tangle.....

generate loop

Are those generic parameters? Or what?

Re: generate loop

yes they are parameters which can change in runtime..... i stuck up here only....how i can instantiate these parameters without using defparameter....

generate loop

If the value of ITERATIONS is dynamic, then there is no way you can do this without LOOP.

If you send the top entity of the block, it will be much easier to answer to your question.

Re: generate loop

here i posted my code, it consists three modules they are signed_shifter, rotater and cordic which is the top entity.....my doubt is in last of cordic module....

module signed_shifter (
input wire [`ITERATION_BITS-1:0] i,
input wire signed [`XY_BITS:0] D,
output reg signed [`XY_BITS:0] Q );
integer j;
always @ * begin
Q = D;
for(j=0;j<i;j=j+1) Q = (Q >> 1) | (D[`XY_BITS] << `XY_BITS);
end
endmodule


module rotator (
input wire clk,
input wire rst,
input wire signed [`XY_BITS:0] x_i,
input wire signed [`XY_BITS:0] y_i,
input wire signed [`THETA_BITS:0] z_i,
output wire signed [`XY_BITS:0] x_o,
output wire signed [`XY_BITS:0] y_o,
output wire signed [`THETA_BITS:0] z_o
);

parameter integer iteration = 0;
parameter signed [`THETA_BITS:0] tangle = 0;

reg signed [`XY_BITS:0] x_1;
reg signed [`XY_BITS:0] y_1;
reg signed [`THETA_BITS:0] z_1;
wire signed [`XY_BITS:0] x_i_shifted;
wire signed [`XY_BITS:0] y_i_shifted;

signed_shifter x_shifter(iteration,x_i,x_i_shifted);
signed_shifter y_shifter(iteration,y_i,y_i_shifted);

always @ *
if (rst) begin
x_1 <= 0;
y_1 <= 0;
z_1 <= 0;
end
else begin
if (z_i < 0) begin
x_1 <= x_i + y_i_shifted; //shifter(y_1,i); //(y_1 >> i);
y_1 <= y_i - x_i_shifted; //shifter(x_1,i); //(x_1 >> i);
z_1 <= z_i + tangle;
end
else begin
x_1 <= x_i - y_i_shifted; //shifter(y_1,i); //(y_1 >> i);
y_1 <= y_i + x_i_shifted; //shifter(x_1,i); //(x_1 >> i);
z_1 <= z_i - tangle;
end
end
assign x_o = x_1;
assign y_o = y_1;
assign z_o = z_1;
endmodule

//Top Entity
module cordic (
input wire clk,
input wire rst,
input wire signed [`XY_BITS:0] x_i,
input wire signed [`XY_BITS:0] y_i,
input wire signed [`THETA_BITS:0] theta_i,

output wire signed [`XY_BITS:0] x_o,
output wire signed [`XY_BITS:0] y_o,
output wire signed [`THETA_BITS:0] theta_o
);

function [`THETA_BITS:0] tanangle;
input [3:0] i;
begin
case (i)
0: tanangle = 17'd11520; // theta = 45.000000
1: tanangle = 17'd6800; // theta = 22.500000
2: tanangle = 17'd3593; // theta = 11.250000
3: tanangle = 17'd1824; // theta = 5.625000
4: tanangle = 17'd915; // theta = 2.812500
5: tanangle = 17'd458; // theta = 1.406250
6: tanangle = 17'd229; // theta = 0.703125
7: tanangle = 17'd114; // theta = 0.351562
8: tanangle = 17'd57; // theta = 0.175781
9: tanangle = 17'd28; // theta = 0.087891
10: tanangle = 17'd14; // theta = 0.043945
11: tanangle = 17'd7; // theta = 0.021973
12: tanangle = 17'd3; // theta = 0.010986
13: tanangle = 17'd1; // theta = 0.005493
14: tanangle = 17'd0; // theta = 0.002747
15: tanangle = 17'd0; // theta = 0.001373
endcase
end
endfunction

wire signed [`XY_BITS:0] x [`ITERATIONS-1:0];
wire signed [`XY_BITS:0] y [`ITERATIONS-1:0];
wire signed [`THETA_BITS:0] z [`ITERATIONS-1:0];
assign x[0] = x_i;
assign y[0] = y_i;
assign z[0] = theta_i;
assign x_o = x[`ITERATIONS-1];
assign y_o = y[`ITERATIONS-1];
assign theta_o = z[`ITERATIONS-1];

genvar i;
generate
for(i=0;i<`ITERATIONS-1;i=i+1) begin:Loop1
rotator U (clk,rst,x,y,z,x[i+1],y[i+1],z[i+1]);
defparam U.iteration = i;
defparam U.tangle = tanangle(i);
end
endgenerate

endmodule

generate loop

Which version of Icarus Verilog are you using? Try to update iverilog using git. It should allow icarus to handle generate constructs.

On ubuntu do:
sudo apt-get purge verilog
sudo apt-get install git-core autoconf gperf flex bison
git clone git://icarus.com/~steve-icarus/verilog
cd verilog
source autoconf.sh
./configure
make
make install

Re: generate loop

my icarus version is 0.9.1....how i can update the present verilog.....could you plz explain in detail...what is roll of git here??

generate loop

Git is used for revision control.
http://en.wikipedia.org/wiki/Git_(software)

Re: generate loop

how we can use Git to update the current icarus.....plz tell me in detail....i could not understand you comments.....or can u tell me how to use the above code without using defparameter and generate loop....