counter question? unsolved errors.

counter question?

hi,somebody helps me. there is some unsolved errors,please correct my codes? Tasks:
Single process. Use wait statement to catch the positive clock flank and variable for count and over (recall that variables are used solely inside processes). and testbench.

library ieee ;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.std_logic_unsigned.all;

entity counter1 is
port( clk: in std_logic;
reset: in std_logic;
enable: in std_logic;
downup: in std_logic;
load: in std_logic;
data: in std_logic_vector(3 downto 0);
overflow: out std_logic;
count: out std_logic_vector(3 downto 0)
);
end counter1;

architecture behav of counter1 is
begin
process(clk, enable, reset)

variable Q: unsigned(3 downto 0);
variable over_count: std_logic;
begin
if reset = '0' then
Q := "0000";
elsif (clk='1' and clk'event) then
if enable = '1' then
if load = '1' then
Q := data;
if downup ='0' then
Q := Q + 1;
elsif downup = '1' then
Q := Q - 1;
end if;
else if
Q = "1111" then
over_count := '1';
end if;
end if;
end if;
end if;
end process;
count <= std_logic_vector(Q);
overflow <= std_logic(over_count);
end behav;

original question:


Universal Counter
There exist many styles to design sequential logic. Even when all of them may behave in the same manner during simulations, each of these styles affects synthesis of the actual hardware in different ways. The task here is to design a loadable, resettable, bidirectional counter in five different ways. Each of them should be simulated to ensure the correctness of the description and finally synthesized.

The requirements are (see also the table below):

* Counting is allowed only when the input enable is '1', otherwise it must be paused. Resetting occurs when the input reset is '1'.
* Counting from 0 to 15 (on the output count) when input down/up is '0', and from 15 down to 0 when the input is '1'.
* On overflow (underflow) the counter must generate '1' on output over and continue with counting from 0 upwards (from 15 downwards).
* '1' on the input load loads the counter parallelly (from input data), the input enable must be '1' at the same time.

Hi,

- I would recommend not to use both numeric_std and std_logic_unsigned packages. Use numeric_std package only.
- As you define variable Q as unsigned and assign port data with type std_logic_vector to it, you have to convert this std_logic_vector to unsigned: Q := unsigned(data);
- The 2 variables are only visible inside the process. You assign the values of them outside the process to other signals.

Devas

thanks,Devas!
It simulates correctly as I change the points you mentioned.