Continue to Site

Welcome to EDAboard.com

Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.

Register Log in

Fixed clock generator using phase accumulator

Status
Not open for further replies.
firefoxPL

firefoxPL

Member level 1
Joined
Mar 18, 2008
Messages
41
Helped
7
Reputation
14
Reaction score
2
Trophy points
1,288
Location
Poznan, POLAND
Activity points
1,521
phase accumaltor

Hello, I would like to present a software I've written for calculating parameters of phase accumulator in order to create a clock with given frequency. The idea of using phase accumulator for this task is taken from an Analog Devices article about Direct Digital Synthesis - the article can be found here.
The whole idea of phase accumulator is very simple, you just add a fixed value to a register (which width is one of the needed parameter) and a clock signal with 50/50 duty cycle is generated with the MSB of the accumulator. And realization of this idea in FPGA takes very few resources so it is perfect for generating precise clock signals from given frequency (usualy from some oscillator on board).
As an attachment I've put the software (you can also find it on my web page) not only for calculating all needed parameters but also for generating a ready to use VHDL code of customized phase accumulator.
If there are any questions about the idea or the program itself please ask here in this topic.
 

Dear firefoxPL

some questions

1- could I get any output for a given input??
what is the constraints on output freq.??

2- I have tried the program for input=50Mhz, output=37.5Mhz , it gives wrong output , could you give me a file making this function??

waiting for your reply
 

To operate the NCO as a digital clock output, the frequency must be surely <= 0.5 fs. In addition, as this is a fractional clock generator, the division ratio must be much higher to keep the output jitter below an acceptable limit for arbitrary frequencies.
 

Re: phase accumaltor

firefoxPL said:
Hello, I would like to present a software I've written for calculating parameters of phase accumulator in order to create a clock with given frequency. The idea of using phase accumulator for this task is taken from an Analog Devices article about Direct Digital Synthesis - the article can be found here.
The whole idea of phase accumulator is very simple, you just add a fixed value to a register (which width is one of the needed parameter) and a clock signal with 50/50 duty cycle is generated with the MSB of the accumulator. And realization of this idea in FPGA takes very few resources so it is perfect for generating precise clock signals from given frequency (usualy from some oscillator on board).
As an attachment I've put the software (you can also find it on my web page) not only for calculating all needed parameters but also for generating a ready to use VHDL code of customized phase accumulator.
If there are any questions about the idea or the program itself please ask here in this topic.
Click to expand...

Hi firefoxPL,

It's nice to see you also implement phase accumulator. I'm currently working with DPLL )

can you please explain to me how an accumulator can adjust the output in-phase with the input signal by changing the K value and keep adding K into itself?

PS: i have download yr file attached, but when i double click on it, there is an error: "The application failed to initiallize properly". Do i need install special software to let it run?
 

Hi cherishnguyen, if I understand you correctly you are wondering how to keep the input (faster) clock of phase accumulator in synch with output (slower) clock of the accumulator.
Basically the output frequency of phase accumulator designed in similar way I did it will always be in-phase with the input signal, because the input signal generates the output clock. So the change in accumulator value (and thus the MSB) will occur synchronously with the input clock. If you want to be sure it is in-phase you could do something like this:
Code: 
signal phaseAcc : std_logic_vector (x downto 0);
signal outClk : std_logic;

process (inClk) is begin
  if(rising_edge(inClk))then
    phaseAcc <= phaseAcc + some_value;
    outClk <= phaseAcc(x);
  end if;
end process;
instead of putting the outClk assignment outside the process. I hope this will be somewhat helpful to you :)
Cheers
 
  • Like
Reactions: douda

    D

    douda

    Points: 2
    Helpful Answer Positive Rating
Status
Not open for further replies.

Similar threads

Part and Inventory Search

Welcome to EDABoard.com

Sponsor

Back
Top