Leakage Current Detector in 1T1C DRAM...Need Help

I am currently doing my 1T1C dram design. My problem is how to detect the leakage current in a standby mode to estimate the refresh period so that the data is not lost in the storage node.
Can you please give me an idea how to attack this problem? Thanks in advance.

Hi there

In a real DRAM 1T1C design you will never have a leakage detection. You just
set the refreshtime according to the minimum spec or, if your process is better,
to a higher refresh time, as this saves a lot of power.
If you want to implement a leakage detection you first need to collect all leakage
contributors, and believe me, there's many of them. The most important ones are
sub-vt leakage of the select device, then we have leakage in the capacitor, and
there might also be leakage in the connection from the select device to the capacitor. One other topic is that the leakage also depends on the charge stored
in the surrounding cells ...
So most of the leakage is hard to get and is strongly driven by technology ...
Good Luck with getting a current sensing into this structure ...
If your models are accurate, you can easily monitor those values in your simulation and choose the proper refresh time according to the amount of
leakage you have.

Best Regards

Andi

You would simply make a "replica" RAM cell and sense
its output voltage against some threshold that ensures
read-margin. When you slump to (say) half threshold,
kick the refresh. Or something.

However, this fails against defect-induced leakage or even
gross leakage mismatch. Expecting one cell to represent
all 16 zillion of its closest friends, isn't realistic.

I forgot one important point which has been implemented
in the latest DRAM designs. Shame on me. As most of the
leakage mechanisms strongly depend on temperature
a temperature dependand refresh is a good idea to
dynamically change the refresh rate. This is spec for DDR3
but I remember that we used that also in some DDR2 designs
Implement as temperature sensor an link it with your self-refresh
counter. Works like a charm in real life

However you still need to characterize the leakage mechanisms
and the statistics that come with the technology.

Best Regards

Andi

Ahanks for the inputs guys.
Andi, if i will decide not to collect the leakage current instead set the refresh time, what is the basis in the estimation of starting the refresh? Is this in relation to the sense amplifier & number of memory cells connected in the bitlines? What other factors will i consider? My problem is how to estimate the refresh time. Can you guide me with this? Can you give reading me reading references? i need your help.

Regards,

Johnny

Hi Johnny

First of all, I'll try to answer your simpler questions I have sent you a PM
regarding some other stuff I need to know before going into more detail, as
I have noticed that my first try to give you an answer got more and more
complex ))

In general you need a spec, wherever this is coming from, JEDEC, a professor
or just your own brain (if doing this as a hobby project)
Unfortunatly I have no real reference book that I can recommend that discribes
Cell-Design in detail (however DRAM Circuit Design from Baker is a good
overview with some details also an array and sense amps). Cell array design
is very complex and most critical to DRAM operation and a lot of stuff is not
published. However I'll try to share some insights

Ok, in nutshell ... Beside the 1T1C cell the most important circuit is the sense-amp
You need to carefully simulate you're sense-amp, and not just one instance of it
There are a lot of effects that need to be considered. You need to include the
extra cap of your bits per bitline as they're adding parasitic cap to the sensing
nodes. This reduces the voltage difference availbale to your sense amp and
therefore this has an indirect effect on the refreshtime. The lower the bitline cap
is, the more leakage can be tolerated because your sense-amp will still get
"enough" signal to work ) In addition to that you need to include the coupling
to the neighbouring bitlines as this cap and also the signaling going on there
affects your sensing signal and therefore this also reduces your signal margin.

Maybe a quick outlook on the refresh time. Depending on what you have available
(cell cap, leakage info) it can just be set to a value according to a spec
(64ms, 128ms,256ms the bigger the better ) and the technology people
"HAVE TO" get the process into a state where this can be fulfilled. So the
prcess itself has the biggest influence on retention and therefore on
selfrefresh time. Maybe one example to make this clear. We designed a
DRAM in a new technology and when the first hardware came back we had
almost no retention beside that we took care of almost all possible effects.
We also did extensive device simulations. However what you see in simulation
is not what you get back on silicion. This is especially true for DRAM's. It took
quite a while until the technology had become so mature and stable that the
spec could be fulfilled, without having done a design change at all !!! I think
that makes it quite clear how important technology is.

Best Regards

Andi

Hi Johnny

Ok, thanks for the additional info. The fact that you'll build your storage array
with MOS-Caps makes life a lot easier
Ok, first we sum up the leakage for a MOS-Cap that have an effect on cell
retention here. The most important ones here will be sub-vt leakage of the
select device and the gate leakage of the storage cap. Ask the technology
people for measured values and collect also the cap/voltage characteristics
of your storage cap. Don't forget that a backbias for cell and selectdevice
can improve the cap value and reduce leakage. After you get those values
build a small model an try to simulate those values to check if leakage and
cap in the model are good enough (sometimes models are not tuned for those
parameters but others ... )
Ok, now we build our sense amplifier. Your sense amp will be the most important
circuit as it is going to decide what info was stored in the cell. As mentioned in
my previous post this needs to be done very carefully. However in your design
the data will not be packed very dense as you will have a big storage cell and
therefore a lot of space for wiring, spacing ... Nevertheless I think it's important
for your studies that you know that if everything is getting smaller the whole
world changes and more effects come into play (bitline-bitline coupling which
might lead to the idea of bitline-twisting), 3d capacitors have more leakage pathes
and so on. Simulate your sense amp with multiple numbers of bit's per bitline
to get a rough idea what happens if your adding more cap to the sense nodes
and how this affects sense amp performance. Here we come to a point where
one has also to decide how much cap for a single cell is needed ... Here you can
make your trade of ...
A smaller storage cap has multiple effects. Layout gets much more compact but
you might have to change bits per bitline and/or refreshtime because the signal
degrades much faster or your senseamp is not able to detect a signal anymore.
A bigger storage cap however gives you a bigger layout but might allow you to
increase selfrefresh time and/or increase the bits per bitline. Here you have
to make up your decision and define the bitline wordline architecture. If you're
making this decision, don't forget to take into account that you can actually build
a selfrefresh that refreshes more then one wordline ... refreshing two wordlines
at the same time halfs selfrefreshtime ... so don't forget this lever
Summing this up, you know how the charge is getting lost, you know what your
senseamp can do and all you have to do now is pick an architecture (bit/bitline,
wordlines, number of senseamp stripes, number of wordlines refreshed at
the same time). Defining such an architecture also has an effect on power
consumption. THe more senseamps (longer wordlines) the more sensecurrent
and also the wordline activationtime goes up, more refresh cycles mean more
powerconsumption ... Whatever you pick has an effect on how you need to set
the refreshtime ...
As I have never done such a DRAM I can't give hints on how to pick, as
the big ones I have been working on have much more limited degrees of
freedom. Cell-Cap is limited by trench or stackcell (around 20fF target value)
and area and power are the main optimisation goals ... all this is giving the
technology people much more headache than circuit designers

However, I would do the following to come up with a target. Simulate
the senseamp with multiple bits per bitline variants and different storage caps.
This gives you a minimum cell level you need to detect a zero or a one. The bits
per bitline together with your 256kB memory size give you a number of wordlines
you need to have. Then I would simulate the single cell with sub-vt and gate
leakage to find how long it takes for the storage cap to reach the values found
as senseamp limits. This basically is your minimum refreshtime and depends of
course how much storage cap per cell you are planing to use. Add some guard-
band to this value and pick a nicely "countable" number close to it
For the selfrefresh logic I would nevertheless recommend something that can
be soft programmed with fuses or testmodes so that, just in case, you can adjust
the selfrefresh time. This gives you the possiblity to increase or decrease the
timing to find limits of your core.

Have fun with your DRAM

Best Regards

Andi

I had a little time to think a little bit about a ASIC implemenation of a DRAM
Maybe it's a good idea to store the information in differential form, meaning
that you spend one extra bit to store the inverted info to a neighbouring cell.
When reading the info you connect the cell and the inverted cell to the sense
amp. This significantly improves signal margin and signal development timing.
It's also not sure that your chip gets bigger, maybe you can decrease the caps
significantly so that you don't need to spend more area at all ...

Best Regards

Andi