HIgh speed analog layout : considerations?

analog layout considerations

Hi ppl...I just wanted a few tips for High speed analog layout considerations...I am laying out a 750Mhz LVDS....

apart from the common considerations like
1. no signal routing over MOS
2. separating noisy signal lines from sensitive nodes etc...
can any one give more..
...like there was one designer who was telling "common centroid is not
reccommended method for high speed analog lyt" (maybe b'cos it inc
RC-par)....

can anyone throw more light :roll:

thx,

analog layouts considerations

well i think that the where ever there is consideration for matching common centroid is the suggest method for the same irrespective of high speed design or low speed design.
while designing the high speed LVDS driver one also need to consider for simultaneous switching noise. and some care must be need to taken for the same during the circuit designing and during the layout also..sufficient decoupling cap must be provided.
shield the reference line from the switching circuit.

if you are having analog circuit along with the high speed digital circuit. care must be taken to avoid the substrate coupling.

Amit

inductor type routing in analog layout

But dont u think common centroid introduces a lot of
parasitics (due 2 extra routing efforts).....wont this affect speed?

rgds,

high speed layout considerations:

The common centroid is one of the approaches that actually is making sure that you will reduce the mismatches caused by PVT(process, voltage, temperature) variations. It doesn't affect the speed. The layout should be symmetrical

high speed analog layout

But dont u think common centroid introduces a lot of
parasitics (due 2 extra routing efforts).....wont this affect speed?

rgds,

Click to expand...

well as far as i think that he parasitic introduce by routing will not be high enough to resonably affect your speed.
plu one more thing bu using the common centroide one can reduce the drain cap also...
Amit

How to u ensure the frequency and the precision?
temerature shift: positive, negative and naught

Because i'm intereseted in the same matter can you tell me where can i find more documentation regarding this problem?
Thank You.
Sime

Unfortunately there are only 2 books that i know of out there. One is CMOS only by Dan Klein the other"the art of analog layout" by hastings
The rest only articles probably and experience. I think the last one was uploaded on elektroda some time ago

yes....most of it is experience as i am finding out now....

for eg: for precision..let's say resistors, u dont bend/finger them (even if they are big)......u also put resistences in their own well to give a quite environment..etc

rgds,

last few chapter of analog design by Razavi are also good refence for the same. Rather i will say they are the best availble.

Amit

If symmetry properties are important for LVDS it is the wiring pattern which is more responsible for mismatches. With common practice of layout for DC offset you improvements of some mV for systematic errors. But at high speed there two effects.

1. The return pathes for the current. Some 100pH could also make some forth mV.

2. Parasitic caps could also introduce asymmetric effects. There is also a layout method to ensure symmetry. Layout only a half of the circuit. The full cell is the same cell mirrored. At some point you get crossings. Here you should use vias which are not full symmetric. Works great with a editor with edit in place.

yes...it's like when we were kids and painting something on a piece of paper. you put some colours/structeres in our case on one half of the paper and then you fold the paper in half.The result..an exactly identical shape on the other side of the paper. . This is probably the best approach in most of the cases

I want to remark that if the number of parallel devices is high also differential finger structures are useful. These could also be layouted with the above method. But the two parts are folded together. In this case it is a little more complicated. The differential finger architecture is steaming from the MOS PAs. In this case differential current does not have to pass the hole size of the structure.

Make sure the high speed lines are routed on top metal to reduce paracitics and pay some attention onthe pads used. For high speed advicable to route the lines in symetical fashion to reduce cross coupling in a balanced stucture. For high speed is normally traded off with mismatch. You can simulated with mismatch and see how the circuit performs and if it less criticle them focus on using short transmission line to reduce paracitics.

For 750 MHz LVDS, try the following suggestions:

The diffpair has to be symmetric and common centriod. The whole stage should preferably be enclosed in a guard ring to separate it from digital stuff, if any.

A guard ring is nothing but a rectangle shaped ground ring over pplus and an nwell over nplus with active regions and connections to ground and vdd respectively.

Also the high frequency signals should be routed over an n-well to reduce substrate noise injection caused by them.

Whenever you use resistors, use dummys on all sides to match the boundary conditions.

Interleave resistors to reduce mismatch between them.

Make sure that every connection from one metal layer to the other has four vias arranged as a square, so that the resistance and inductance is reduced. otherwise at 750Mhz, there will be a delay associated with every via.

Also to ensure a good ground (necessary for highspeed links), slot the ground plane to make a mesh grid pattern, so that there is no localized eddy currents flowing.

Put a capacitor between vdd and vss ( the decoupling cap) calculate using the typical inrush current at startup.

Also use an inductor between vdd and the top pmos(es) to reduce vdd noise coupling. This alone reduces the phase noise in oscillators by about 4dB and is a well known technique. Ask someone for more advice.

use an inductor between vss islands so that a localized disturbance at one ground plane does not immediately affect the ground at another point.

Use ground contacts, each contact has a typical resistance of ~1 ohm for new submicron technologies. use as many as you can for guard rings.

Avoid poly routing except for tracks less than 5um.

For all your transistors, the gate should be connected on both sides to the input, forming a ring. (using poly if desired). Read more about this technique in Razavi's analog design book. This reduces the gate resistance and helps at high frequencies.

For signals going to a sensitive block, land them first, on top of an n-well and then use a via-bridge and then take them further. This helps to reduce unwanted coupling between block.

An advantage of a guard ring is that supplies can be routed to the block efficiently and the resistance is reduced, compared to a tree or a comb structure.

Whenever signals are splitting, try to make a small metal hexagon and then split the signals. (N.B. this is a veryhigh frequency technique). Try not to make y-shaped splits.

Slot the power supply lines in the direction of the current flow to reduce the risk of electron migration and increased resistance which is normally not extracted by any tool.

Other major techniques can be found in the books mentioned by other participants.

Have fun.

1.Could anyone pls. tell me why we go for common centroid matching
when vt of transistors should be matched.why can't we go for interdigitation type?

2.for current matching(id) when we do interdigtation method,can we abut the transistors?.Is it must that the movement of minority carriers from source to drain should be same for the matching transistors?

who have LVDS cable model ( DVD rw pick-up head cable )
I measure real LVDS signal have "overshoot /undershoot"
but in spice I use delay-line , waveform is very good ..

by the way , have anyone simulation eye pattern for LVDS ?

Which process is used for this 750MHz LVDS?

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maybe can help someone to understand...