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1 Hz CMOS Clock Design

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florescent

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clock 1hz

Dear All.

After spending painful times to find some info about 1 Hz clock, I have finally decided to ask this to you all experts.

I am using 0.5um CMOS process in Cadence. For my chip design in biomedical applications, I need to have a 1Hz clock. By the circumstance of its use, I need it with low power consumption, and ON CHIP design.

I have designed a 1.3MHz VCO. If based on this, it requires a 20bit counter for 1Hz. It does not seem to be practical; not only the higher bit, but power consumption point of view too.

Any method or design idea please?

Thank you very much for your any comment.
 

cmos clock

I remember that in CMOS quartz watch chips, the frequency divider uses a different logic design for the first few flip-flops to save power. I cannot remember the name but it may be charge-based logic or differential logic. Sorry I can't be more helpful but it's a start.
 

clock de 1hz

snafflekid said:
... it may be charge-based logic or differential logic.
Click to expand...
florescent said:
I am on search for the stuff you mentioned.
Click to expand...
Perhaps this PDF may be helpful?
 

1 hz oscillator

You can think of using TSPC dffs and some low power techniques.
 

how to design a 1hz frequency rc oscillator

I think the true single phase clock techniques are what you need at the beginning of the chain. They are dynamic and need the transitions to keep refreshed, then at some point you use static CMOS logic.

look for a book called Low-Power CMOS Circuits by CRC press
 

cmos clock design

I would recommend simple relaxation oscillator. Since you are doing it for medical that is the way - all the other approaches are high current.
For 1 Hz you can use few nA charging current, very low power opamp or voltage comparator.
In total you should be able to sqeeze it into 1uA current max.
But I would say that even 1uA is a bit high for you.
Also - you would not get nice 50% duty cycle - so design it for 2hz and divide down.
Across PVT you can get about 15% precision with no trim.
Good luck
 

1hz relaxation oscillator

Actually, all of them are good idea. Thank you all.

Dear Teddy, I have already made an relaxation oscillator for another purpose, but I've never known that it can be operated with 1uA current because I optimized my Relax. OSC for low power consumption, but it still needed around 35uA.

How could you achieve 1uA, but still in operation?
 
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no hz dynamic clock

florescent said:
How could you achieve 1uA, but still in operation?
Click to expand...
Load a 100 .. 200fF cap by a constant current of 0.5µA (or less). A comparator with equivalent current consumption controls a short-circuit transistor in parallel to the cap. A following FF provides 50% duty cycle.

For a 15 kHz output frequency, I got a 500nA w.c. current consumption @ VDD=2.5V .
 

how to do 1hz clock

I partially agree with erikl.
The only point I disagree is the value of the cap. 200fF is way too close to the parasitic capacitance of the surrounding FETs so the FET process variation would be affecting the circuit too much. For 1 Hz I would use 0.5pF-1pF charged with 100nA or so. Since comparator could be very slow use biasing of 250nA.
For voltage reference - same thing. The most current consuming part will be the output structure - so be careful to current limit that one. And if you spend enough time you will get it. I got 7uA osc. @ 3MHz. all @ 0.5um CMOS.
The main thing - keep it simple. Use 1 charging current, cap, comparator and that is it - more complexity more power.
If you want send me the osc. you already have and I can glance at it. From experience I would say - if you have to you will make it.
 

clock buffer ic 1hz

Couldn't you use a chain of CMOS inverters as your comparator? It would save the power of the voltage reference.
 

cmos 1hz generator

Teddy said:
the value of the cap. 200fF is way too close to the parasitic capacitance of the surrounding FETs so the FET process variation would be affecting the circuit too much.
Click to expand...
@ Teddy: I forgot to mention my proc.tech. was 0.18µm. The load cap 137fF, and the comp. input 30fF incl. parasitics - rather huge for this tech. - but constant. And the load current 2bit-controllable. The reset fet was min-sized. The FF for the 50% duty cycle needed about 20% of the overall current consumption.

@ JoannesPaulus: I tried this before, but the first 2 stages of the (min-size) inverter chain burnt a lot more (cross-) current than the 200nA comparator. The comparison voltage was the current generator's bias.

Cheers, Erikl.
 

how to obtain 1 hz clock

FF is not a must. try to make 50% duty cycle without that!!

btw: Do u have trim available(will u current accurate)? since u r doing medical stuff, then the comp is not a must. u can use vt if properly stuctured.
 

1hz clock with inverter

I see "erikl" and "Teddy" are in the same page. Based on the design I attach here, I can now achieve less than 4uA current consumption at 2.5 VDD under 0.5um CMOS.

Now, I am working on Relaxation OSC.
 

Attachments

  • selfb_comp.fold.cascode.anam_1767.pdf
    207.8 KB · Views: 172

oscillator 1 hz simple

Less 1uA was achieved in 1/16 Hz oscillator in 0.35um technology. Structure was: 8KHz 3-stage ring oscillator (<0.3uA) with special current bias circuit, and 17-stages binary counter, where first 7 stage were supplyed from built-in voltage regulator with reduced supply voltage.
 

cmos clock oscillator driver circuit -patent

Dear mikersia

What VDDs did you use to get your results?

What could be the special bias circuit?

I can't supply enough power to the circuit since mine is a wireless feeding mechanism at a very low frequency. If 10 stages of your binary counter were fed by an external supply source, it might not be for my case.

Thank you
 

oscillator consumption 1ua

binary counter should not be a big deal for power consumption - you should not look at max peaks but average or RMS current. That will be really low if you divide down kHz signal.
 

1hz counter

to florescent

all design was designated for 2.5...3.6V supply range
Voltage regulator for buffer stage of oscillator and 7 cascades of divider provides (Vgs_nmos+Vgs_pmos).
Bias circuit generates current supplying ring oscilator, which is also compensating PVT mismatch, and providing frequency to be ~1/RC only.
10 stages of binary counter with full system supply voltage require a neglectable average current, as mentioned Teddy
 

one hertz clock

I've got a 1hz ring osciallator based on VCO. It draws 0.8uA or 1.7uA depending on size of caps.

I deeply appreciate all your helps
 

how to design flip-flop sizing mos

Consider a switched current source, limit-comparator design
ala the venerable LM555. Or switched resistors if you can stand
the area. The current source linearly ramps a timing cap, set
the comparators to (say) 1/4 and 3/4 VDD, flip to discharge
when you go above 3/4 and charge when it gets down to 1/4
(S-R FF will eliminate chatter and hold the state). You will have
tolerances to deal with on capacitors (probably 10%), current
(maybe you already have a usable reference you can tap).
You would need to stay up out of the leakage floor but 1uA
current ought to be plenty safe and even 10nA doable with
longer channel current sources and switches.

If you have to do better than 10% envelope of accuracy you
probably need a resonator or crystal reference. Old digital
watches used 32768 Hz crystals so you'd need fewer stages,
and slower, of divider. Maybe the newer ones still do, I dunno.
 

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