Which is correct way to measure max frequency

verilog measuring period

Dear Folks,
I synthesized AES (Advanced Encryption Standard) verilog core that i downloaded from www.opencores.org. For synthesis i used Synopsys Design compiler and tsmc180nm library. During synthesis, i specified the clock period constraint to be 5ns or (200 MHZ) and Design Compiler showed no violation of the period constraint during synthesis.

After synthesis, i did post synthesis verilog simulation. Here i started getting setup and hold time violations with 5ns clock period and had to increase clock period by a factor of 40 i.e. 200ns (5 MHZ) to get valid results.

I am confused either post synthesis frequency of 5 MHZ is the true frequency of the design or pre synthesis frequency of 200 MHZ is the true frequency of the design.

I also did PrimeTime static timing analysis of the design after synthesis and it also had no problem with the period constraint of 5ns.

I must mention that post synthesis verilog simulation of the design is dynamic one that is you have to give test_vectors in a test bench to get outputs while primetime and design compiler using static timing methods without any test vectors to report the maximum frequency.

Thanks for your help.

verilog code frequency measure

Are your STA contraints complete. Did the SDF annotate correctly? Did you try reporting the same path in PT that you see the violation on in the simulation? How do they compare?

measure max

I am getting this error in post synthesis verilog simulation of AES core. DC synthesized the design correctly without any errors with a period constraint of 5ns( 200 MHZ)

But i am running post synthesis verilog simulation with a period of 20ns and i still get this error because of which the output is xxxxxxxxxxxxxxxxxxxxxxx.

Error: tsmc18t.v(6551): $hold( posedge CK &&& (flag == 1):30 ns, negedge D:30 ns, 500 ps );
# Time: 30 ns Iteration: 2 Instance: /test/u0/u0/r0/\out_reg[31]


Any idea how to fix this error?


Thanks a lot in advance

max frequency sta

Two reasons :

1. You are constraints are not full or wrong during synthesis and STA

2. Check for the same path wher it has violated the HOLD in the STA as well so that you can double check whether it has taken the same delay as that of gate level simulation. i.e compare the. delays from STA and gate level simulation(netlist + SDF).

It can be that your SDF file was not generated properly.

the measure of frequency

I am not doing sdf generation at this stage. How to know whether your constraints are full or not?

true frequency

with out using SDF for gate leve simulation, you are trying to compare Apples with Oranges. Dont compare the results with STA and gate level simulation.

To check whether your constraints are complete or not, its a detailed process. somebody has to know about your design and special things inside your design, where we can apply multicycle paths, false paths. If your design doesnt have this kind of special schemes, put your interface and constarints. somebody can help you out what is missing in your constraints.

how to measure frequency + verilog

dcredddy! Could you tell why sdf is needed in post synthesis simulation?

specify sdf overwrite verilog

without back annotating SDF file to your gate level simulation, how can you get your exact gate delays. These gate delays which you see in your simulation must be identical to what you will seeing in the STA for that particular PVT.

dcreddy!
I have the verilog file tsmc018.v which is needed in post synthesis simulation. I am attaching it so that you could see it. Doesn't it have the delay or the timing information of the gates? I mean whats unique about sdf file.


Thanks

The verilog file which u have attached will only have soem default delays for the cells. If we have SDF file of any design, the delay information from these SDF files will overwrite the cell delays specified in the given verilog file.

For example : in your design, you are using AND gate with a delay of 100 ps and another AND gate with a delay of 200 ps.

How do you want to tell the exact delays of your design.

dcreddy1980, You are simply awesome.

Thanks a lot for sharing your insight.

u can try this command in ur script : set_fix_hold

btw, it's better to fix the hold problems in post end