DFT errors when trying to insert scan chain to a design

Hi, I am trying to use DFT compiler to insert scan chain to the design, but there are some errors, and I can not find out the reason.
In this design, there are two clocks and I want to add 6 scan chains in it.
The errors are shown below.

Information: Starting test design rule checking. (TEST-222)
Loading test protocol
...basic checks...
...basic sequential cell checks...
...checking vector rules...
Error: illegal context (Procedure "multiclock_capture" is missing design clock "data_source" in clock parameters). (V8-1)
Error: illegal context (Procedure "allclock_capture" is missing design clock "data_source" in clock parameters). (V8-2)
Error: illegal context (Procedure "allclock_launch" is missing design clock "data_source" in clock parameters). (V8-3)
Error: illegal context (Procedure "allclock_launch_capture" is missing design clock "data_source" in clock parameters). (V8-4)
Error: miscounted items (Force clocks has 3 values instead of 4 in procedure "multiclock_capture"). (V10-1)
Error: miscounted items (Force clocks has 3 values instead of 4 in procedure "allclock_capture"). (V10-2)
Error: miscounted items (Force clocks has 3 values instead of 4 in procedure "allclock_launch"). (V10-3)
Error: miscounted items (Force clocks has 3 values instead of 4 in procedure "allclock_launch_capture"). (V10-4)
Error: Could not perform design rule checking. (TEST-1311)
0

The scripts for DFT is shown below.
Are there any mistake there, please?


#specify test components in preparation for creat_test_protocol
read_file -format ddc mapped/compile_top.ddc

create_port -direction "in" {Reset TEST_MODE}

set_dft_signal -view existing_dft -type ScanClock -timing {4.5 5.5} -port clk
set_dft_signal -view existing_dft -type ScanClock -timing {4.5 5.5} -port wb_clk_lower
set_dft_signal -view existing_dft -type Reset -active 0 -port Reset
set_dft_signal -view existing_dft -type Constant -active 1 -port TEST_MODE

set_scan_configuration -clock_mixing mix_clocks

set_scan_configuration -style multiplexed_flip_flop

set_scan_configuration -chain_count 6

#From the above spectifications, create the test protocal

create_test_protocol

#check the test-protocol

dft_drc

#write out the test protocol

write_test_protocol -output reports/protocol.spf

compile_ultra -num_cpus 4 -scan

#autofix

#set the signal to use
set_dft_configuration -fix_clock enable -fix_reset enable -fix_set enable
set_dft_signal -type TestMode -port TEST_MODE
set_dft_signal -type TestData -port clk
set_dft_signal -type TestData -port wb_clk_lower
set_dft_signal -type TestData -port Reset

#set the type to autofix
set_autofix_configuration -type clock -test_data clk -control_signal TEST_MODE
set_autofix_configuration -type clock -test_data wb_clk_lower -control_signal TEST_MODE
set_autofix_configuration -type set -test_data Reset -control_signal TEST_MODE
set_autofix_configuration -type reset -test_data Reset -control_signal TEST_MODE

preview_dft
insert_dft
dft_drc
report_scan_path -chain all

#finnal work

change_names -rule verilog -hierarchy

#check result
report_dft > reports/dft
report_scan_configuration > reports/scan_config
report_dft_signal -view existing_dft > reports/dft_signals
report_scan_path -view existing_dft -chain all > reports/scan_chains
report_scan_path -view existing_dft -cell all > reports/scan_cells

#hand off
set test_stil_netlist_format verilog
write -f verilog -h -o mapped/top.v
write_test_protocol -o mapped/top_SCAN.spf

#Save design
write -format ddc -hierarchy -output mapped/top.ddc


Thank you!
Best regards!

due to design rule checking error dft

Why did you add this in your script ??


set_dft_signal -type TestData -port clk
set_dft_signal -type TestData -port wb_clk_lower
set_dft_signal -type TestData -port Reset


clocks & resets are Testdata signals in your design or what ??

Added after 1 hours 55 minutes:

it should be

-type ScanClock
-type Reset

test_fix_bus

use
create_test_protocol -infer_clock
-capture_procedure multi_clock

multi_clock will create a protocol file which uses generic capture procedures for all capture clocks.

asic-dft.com

Added after 3 hours 25 minutes:

Hi jaydip,

For some test signals, we need to add "set_dft_signal -type TestData -port Reset" as well. This way v r informing the tool that these signals can be used for auto fixes.

asic-dft.com

fix drc error dft

Hi sunilbudumuru
Thank you for your reply.
I have tried that command.
create_test_protocol -infer_clock -capture_procedure multi_clock

The errors above have been solved. But another error came out.

dc_shell> dft_drc -coverage_estimate
In mode: Internal_scan...
Design has scan chains in this mode
Design is scan routed
Post-DFT DRC enabled

Information: Starting test design rule checking. (TEST-222)
Loading test protocol
...basic checks...
...basic sequential cell checks...
...checking vector rules...
Error: illegal context (measure_sco must be the last event in procedure "shift"). (V8-1)
Error: Could not perform design rule checking. (TEST-1311)
0
dc_shell>

I have found the user_guide, but there no any message about the measure_sco, what should I do to solved this error, please?

Thank you!
Best regards!


Hi jaydip,
The defines above are right I think, and they are the same as the user_guide sample.

Thank you for your message.

site:www.edaboard.com gaom9

set_dft_signal -view existing_dft -type Reset -port Reset
try this
I think U use reset port as data port

dft compiler reset constant

Hi, HolySaint
Thank you for your reply. In the script above, I have added the command as:
set_dft_signal -view existing_dft -type Reset -active 0 -port Reset
and as sunilbudumuru said above, I define the Reset port as a TestData using in autofix. I saw this define in DFT compiler user guide.
Is there any matter with this define, please?

Thank you!
Best regards!

test_default_strobe in dft

gaom9 said:

Hi, HolySaint
Thank you for your reply. In the script above, I have added the command as:
set_dft_signal -view existing_dft -type Reset -active 0 -port Reset
and as sunilbudumuru said above, I define the Reset port as a TestData using in autofix. I saw this define in DFT compiler user guide.
Is there any matter with this define, please?

Thank you!
Best regards!

Click to expand...

sorry, i didn't see the dft signal u had set.

about the autofix option, i didnt so clear . i will try later to test ur sets

verilog compiler error miscounted events

Hello friends,

U have to mention DFT signals (mandatory).
For autofix, mention "testdata" signals. So that the tool will consider the test data signals for the purpose of auto fixing.

asic-dft.com

existing_dft spec

Hi, sunilbudumuru

Do you know why the new error above came out? Is there any mistake in my script setting?

Thank you.
Best regards!

set_dft_signal hookup_pin

Hello Friend,

Use the following test timing setup before the protocol.

test_default_delay = 0
test_default_bidir_delay = 0
test_default_strobe = 4
test_default_period = 10
test_stil_multiclock_capture_procedures = true

Pls. upadte if it worked or not.

asic-dft.com
sunil budumuru

procedure multiclock_capture

i did it successfully by ur script to fix test_clk

so i think what u set is right.

what about adding what sunilbudumuru said

i had added

compile_ultra error

Hi, sunilbudumuru
I have tried your advice. But the some errors still came out...

Information: Starting test design rule checking. (TEST-222)
Loading test protocol
...basic checks...
...basic sequential cell checks...
...checking vector rules...
Error: illegal context (Procedure "multiclock_capture" is missing design clock "data_source" in clock parameters). (V8-1)
Error: illegal context (Procedure "allclock_capture" is missing design clock "data_source" in clock parameters). (V8-2)
Error: illegal context (Procedure "allclock_launch" is missing design clock "data_source" in clock parameters). (V8-3)
Error: illegal context (Procedure "allclock_launch_capture" is missing design clock "data_source" in clock parameters). (V8-4)
Error: illegal context (measure_sco must be the last event in procedure "shift"). (V8-5)
Error: miscounted items (Force clocks has 4 values instead of 5 in procedure "multiclock_capture"). (V10-1)
Error: miscounted items (Force clocks has 4 values instead of 5 in procedure "allclock_capture"). (V10-2)
Error: miscounted items (Force clocks has 4 values instead of 5 in procedure "allclock_launch"). (V10-3)
Error: miscounted items (Force clocks has 4 values instead of 5 in procedure "allclock_launch_capture"). (V10-4)
Error: Could not perform design rule checking. (TEST-1311)



Thank you!
Best regards

measure_sco

Okay...

1. remove "test_stil_multiclock_capture_procedures = true" from the following.

test_default_delay = 0
test_default_bidir_delay = 0
test_default_strobe = 4
test_default_period = 10
test_stil_multiclock_capture_procedures = true



2. Also replace your "set_scan_configration" with the following:
set_scan_configration -chain_count 6 \
-add_lockup true \
-internal_clocks multi \
-clock_mixing mix_clocks \
-style multiplexed_flip_flop

As u r using multiple clocks and we are mixing the clocks it makes sense to add lockups. Just try replacing your "set_scan_configration " with the above switch.

3. Pls. try set the following variable at the begining of the script
"set test_fix_bus true"

And update the results.

asic-dft.com

set_autofix_configuration

I am sorry it took a few hours to finish the work.
The error is still there...

========================================
TEST MODE: Internal_scan
VIEW : Existing DFT
========================================

========================================
AS SPECIFIED BY USER
========================================


========================================
AS BUILT BY insert_dft
========================================

Scan_path Len ScanDataIn ScanDataOut ScanEnable MasterClock SlaveClock
----------- ----- ----------- ----------- ----------- ----------- -----------
I 1 11501 test_si1 flash_a[20] test_se jtag_tck -
- clk -
I 2 11500 test_si2 test_so2 test_se clk -
I 3 11500 test_si3 test_so3 test_se clk -
I 4 11500 test_si4 test_so4 test_se clk -
I 5 11500 test_si5 test_so5 test_se clk -
I 6 11500 test_si6 test_so6 test_se clk -
- jtag_tck -
- wb_clk_lower -

In mode: Internal_scan...

Design has scan chains in this mode
Design is scan routed
Post-DFT DRC enabled

Information: Starting test design rule checking. (TEST-222)

Loading test protocol
...basic checks...
...basic sequential cell checks...
...checking vector rules...
Error: illegal context (Procedure "multiclock_capture" is missing design clock "data_source" in clock parameters). (V8-1)
Error: illegal context (Procedure "allclock_capture" is missing design clock "data_source" in clock parameters). (V8-2)
Error: illegal context (Procedure "allclock_launch" is missing design clock "data_source" in clock parameters). (V8-3)
Error: illegal context (Procedure "allclock_launch_capture" is missing design clock "data_source" in clock parameters). (V8-4)
Error: illegal context (measure_sco must be the last event in procedure "shift"). (V8-5)
Error: miscounted items (Force clocks has 4 values instead of 5 in procedure "multiclock_capture"). (V10-1)
Error: miscounted items (Force clocks has 4 values instead of 5 in procedure "allclock_capture"). (V10-2)
Error: miscounted items (Force clocks has 4 values instead of 5 in procedure "allclock_launch"). (V10-3)
Error: miscounted items (Force clocks has 4 values instead of 5 in procedure "allclock_launch_capture"). (V10-4)
Error: Could not perform design rule checking. (TEST-1311)

set_autofix_configuration

if possible could you please provide your entire script to my mail ID?

sunilbudumuru(at)gmail.com

i'll suggest step by step procedure to handle the issue. This kind of issues can be handled easily. A small mistake can make a big difference.

Before that u can try this flow.

Pls ans the following.

Is this test-ready design?

Sunil Budumuru

Added after 3 hours 38 minutes:

Dear Friend,

U can try the following flow.


read_file -format ddc mapped/compile_top.ddc

Current_design xxxxxx
Link
compile_ultra -num_cpus 4 –scan

create_port -direction "in" {Reset TEST_MODE}

Current_design xxxxxx
Link
change_names -rules verilog -verbose -hierarchy
write -f verilog -h -o mapped/scan_replaced.v

# DFT variable declaration
set test_default_period 10
set test_default_bidir_delay 0
set test_default_delay 0
set test_default_min_fault_coverage 98
set test_default_scan_style "multiplexed_flip_flop"
set test_default_strobe 4
test_stil_multiclock_capture_procedures = true

set_scan_configuration -chain_count 6 \
-add_lockup true \
-internal_clocks multi\
-clock_mixing mix_clocks \
-style multiplexed_flip_flop

##############scan path #############

set_dft_signal -view spec \
-hookup_pin [get_pins p0in_pad/DI] \
-port [get_ports Pin_PAD] \
-hookup_sense non_inverted \
-type ScanDataIn

set_dft_signal -view spec \
-hookup_pin [get_pins p0out_pad/DO] \
-port Pout_PAD \
-hookup_sense non_inverted \
-type ScanDataOut

set_scan_path chain0 -view spec \
-scan_data_in [get_ports Pin_PAD] \
-scan_data_out [get_ports Pout_PAD]


set_dft_signal -view existing_dft -type ScanClock -timing {4.5 5.5} -port clk
set_dft_signal -view existing_dft -type ScanClock -timing {4.5 5.5} -port wb_clk_lower
set_dft_signal -view existing_dft -type Reset -active 0 -port Reset
set_dft_signal -view existing_dft -type Constant -active 1 -port TEST_MODE

set_dft_signal -view existing_dft \
-port [get_ports [list TEST_MODE]] \
-hookup_sense non_inverted \
-type TestMode \
-active_state 1
set_dft_signal -view spec \
-port [get_ports [list TEST_MODE]] \
-hookup_sense non_inverted \
-type TestMode \
-active_state 1


#autofix

#set the signal to use
set_dft_signal -type TestMode -port TEST_MODE
set_dft_signal -type TestData -port clk
set_dft_signal -type TestData -port wb_clk_lower
set_dft_signal -type TestData -port Reset



set_dft_configuration \
-fix_bidirectional disable \
-scan enable \
-fix_clock enable \
-fix_set enable \
-fix_reset enable

set_autofix_configuration -type clock \
-include_elements [get_object_name [all_registers ] ] \
-method mux \
-control_signal TEST_MODE \
-test_data wb_clk_lower





set_autofix_configuration -type clock \
-include_elements [get_object_name [all_registers ] ] \
-method mux \
-control_signal TEST_MODE \
-test_data clk

set_autofix_configuration -type reset \
-method mux \
-control_signal TEST_MODE \
-test_data Reset

set_autofix_configuration -type set \
-method mux \
-control_signal TEST_MODE \
-test_data Reset



######## Test Protocal creation ######################
create_test_protocol -infer_clock -capture_procedure multi_clock

write_test_protocol -out protocol.spf

dft_drc -pre_dft -verbose > reports/dftdrc_prescan.rpt

################ preview dft ###########################
preview_dft -test_points all > reports/preview_dft_tp.rpt
preview_dft -show all > reports/preview_dft_all.rpt

################ Stritch the Scan Cells #################
insert_dft

# postscan drc
dft_drc -verbose > reports/dft_drc_postscan.rpt

# output netlist
change_names -rules verilog -verbose -hierarchy
write -f verilog -h -o output/top_postscan.vs

write_scan_def -o vpc_top.def

# coverage
estimate_test_coverage -sample 99 > reports/dft_coverage.rpt

pls update the results.
asic-dft.com

Added after 3 minutes:

once u r done with the above run, from next time onwards, u can use "scan_replaced.v"
to avoid your compile.

Just read the scan replaced netlsit and do the R&D on that.

dft errors

if u wanna test the script is right or not,u can use a small design

it takes a little time, and u can see the rslt quickly

if the flow is right,maybe there is mistake in ur netlist that u read in..

hope it helpful

compile_ultra num_cpus

Hi, sunilbudumuru

Thank you. Good news! I have finished the single clock DFT synthesis, and the coverage_estimate result is as follow.

Now I am trying the multi-clock DFT synthesis.

Hope good news again.

Best regards!

Uncollapsed Stuck Fault Summary Report
-----------------------------------------------
fault class code #faults
------------------------------ ---- ---------
Detected DT 1756859
Possibly detected PT 0
Undetectable UD 128179
ATPG untestable AU 293
Not detected ND 463
-----------------------------------------------
total faults 1885794
test coverage 99.96%
-----------------------------------------------
Information: The test coverage above may be inferior
than the real test coverage with customized
protocol and test simulation library.
1

Added after 11 minutes:

Good news again.
I have finished the multi-clock DFT synthesis. And the result is shown as:


Uncollapsed Stuck Fault Summary Report
-----------------------------------------------
fault class code #faults
------------------------------ ---- ---------
Detected DT 1756683
Possibly detected PT 1
Undetectable UD 128137
ATPG untestable AU 435
Not detected ND 514
-----------------------------------------------
total faults 1885770
test coverage 99.95%
-----------------------------------------------
Information: The test coverage above may be inferior
than the real test coverage with customized
protocol and test simulation library.
1

Best regards!

dft rule error

Great Gaom, lets see how it goes with multi clock.

asic-dft.com

Added after 3 minutes:

Ohh great Gaom,

pease post the scripts (both single and multi clock) here that I've modified and provided to you. That may be helpful to others.

asic-dft.com
sunil budumuru

allclock_capture

Powerful DFT sctipts by sunil budumuru.

Best regards!

hookup_pin dft drc

Hello friend,

Its not powerful... its just workable scripts....

Cheers,
asic-dft.com