:? Verilog Pulse Generator

 `timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:        Allied Electronics Co.
// Engineer:       K.V.Mahesh
// 
// Create Date:    00:38:39 05/24/2009 
// Design Name:    Dual Pulse Generator
// Module Name:    Pulse_Gen 
// Project Name:   Dual Pulse Generator
// Target Devices: XC3S400A FT256 -4 Speed Grade
// Tool versions:  10.1i
// Description:    This is a Pulse Generator Module that generates a Pulse on the negative edge 
//                 of the trigger signal.The Pulse_Width word is from the main module.
//
// Dependencies:   Main.v
//
// Revision:       v0.6
// Additional Comments: 
//
//////////////////////////////////////////////////////////////////////////////////
module Pulse_Gen(
    input Trigger,
    output Pulse_Out,
    input [31:0] Pulse_Width,
    input Clock
    );
	 
//////////////////////////////////////////////////////////////////////////////////	 
//Register Declaration.																			  //
//////////////////////////////////////////////////////////////////////////////////
reg[31:0] PWidth;                              //To Hold Pulse Width Word.
reg Out_Enable;                                //For Triggering Purposes.
reg Pulse=0,Done;

//////////////////////////////////////////////////////////////////////////////////
//Triggering																						  //
//////////////////////////////////////////////////////////////////////////////////
always@(posedge Trigger)
 begin
 Out_Enable=~Out_Enable;
 end

//////////////////////////////////////////////////////////////////////////////////
//Actual Pulse Generation Section															  //
//////////////////////////////////////////////////////////////////////////////////
always@(posedge Clock)
 begin
 if(PWidth==Pulse_Width)
  begin
   PWidth<=32'h00000000;
	Pulse<=1'b0;
  end
 else
  begin
   PWidth<=PWidth+1;
   Pulse<=1'b1;
  end 	
 end
 
assign Pulse_Out=Pulse;

endmodule

module pulse_gen
 (
   input        Trigger,
   output       Pulse_Out,
   input [31:0] Pulse_Width,
   input        Clock
 );
   
reg [1:0] trig;

always @(posedge Clock)
 trig <= {trig[0],Trigger};

wire ld_cnt = (trig == 2'b01) ? 1'b1 : 1'b0;
 
reg [32:0] cnt;

always @(posedge Clock)
  if      ( ld_cnt )   cnt <= {1'b1,Pulse_Width};
  else if ( !cnt[32] ) cnt <= cnt;
  else                 cnt <= cnt - 1'b1;
  
assign Pulse_Out = cnt[32];

endmodule