Decoupling caps - how to calculate the amount of on-chip

Decoupling caps

Hi !

Can someone tell me how to calculate the amount of on-chip
Decoupling caps required for a mixed signal block like DAC and
ADC.

TIA

Ragduga

Decoupling caps

Usually Input/Output on regulator. Close as possible to ICs and any other sensitive components. No sure if you can calculate it by any means though. I generally use .1uf, with smaller .001s if r.f a problem.

Re: Decoupling caps

raduga_in said:

Hi !

Can someone tell me how to calculate the amount of on-chip
Decoupling caps required for a mixed signal block like DAC and
ADC.

TIA
Ragduga

Click to expand...

Hi Raduga,

that's how I usually try to do that: Assuming a reasonable power supply output impedance, I get an RMS value superimposed on VDD. With the PSRR value (at the relevant frequency) and the necessary resolution of my converter, I calculate the admissible VDD RMS value, from that the necessary filter capacitance.
Usually, I get much too high values, which I can't afford :-( So I'm used to fill every empty space in each cell - and later every empty space between them - with VDD-VSS filter caps, normally as gate caps because of their relatively high capacitance (hoping this won't deteriorate my reliability resp. yield too much because of possible defects - it's quite a lot of real estate - and so results in quite a nice cap value ;-) ). And even if this mostly is lower than my estimated value (s.a.), I always wonder why, e.g., a 10bit-converter still results into a 9bit-converter, and not into an 8bit-converter as feared the worst before ;-)

Cheers, erikl

Decoupling caps

Sorry I misread your question, did not notice you meant non discrete. Looks like you got your answer now anyway.
Doh!