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wat is level triggering of a clock?

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Mkanimozhi

Mkanimozhi

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level triggering

Hi,
wat is level triggering of a clock, how to write a code in vhdl,some one pleae give me some example.


regards
kanimozhi.m
 

Re: level triggering

Hi...
Level triggering is nothing but Latches,

process (enable, data_in)
begin
if enable = '1' then
q <= data_in;
end if;
end process;
 

    Mkanimozhi

    Mkanimozhi

    Points: 2
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Re: level triggering

I guess you mean a level-sensitive latch (which passes input signal to output when clock signal is '1' and holds previous value when clock is '0').

VHDL description of latch:

Code: 
process (CLK,DIN) is
begin
	if CLK='1' then
		DOUT<=DIN;
	end if;
end process;
 

    Mkanimozhi

    Mkanimozhi

    Points: 2
    Helpful Answer Positive Rating
Re: level triggering

Why do you want to go for a level triggered latch,
I guess these are the least wanted in a good logic design.
 

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