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advantages between N+ diffused and P+ diffused resistor?

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bharatsmile2007

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diffused resistor

what are the advantages and disadvantages between

N+ diffused resistor
P+ diffused resistor

Thanks
Bhanu
 

advantages odiffusion resistors

Typically, for a p-substrate/n-well process, the P+ diff. resistor has a (little bit) lower resistivity (Ohm/sq). The N+ diff. resistor - in contrast - typically has a (10 .. 20%) lower TC (both have pos. TC). The N+ diff. resistor has a small positive VC (voltage coefficient), whereas the P+ resistor has a much higher, but negative VC.

HTH, erikl
 

advantages diffusion resistor

Thanks for the information...erikl

as per noise, which one will have more..N+ or P+ diffusion resistor?
 

implementation of resistor in beta multiplier

bharatsmile2007 said:
as per noise, which one will have more..N+ or P+ diffusion resistor?
Click to expand...

No noise parameters available for these resistors, sorry. It's likely that additional noise (to the theoretical R noise) is dominated by picked-up noise from the environment (substrate or well). So use a guardRing if necessary.
 
anvantages of n-well

Thanks for the information...

i have a two types of resistors,for my beta multiplier for biasing my opamp

N+ diffusion with TC 1290PPM with VC 0

P+ difusion with TC 1290PPM with VC 0

understanding what are the advantages/disadvantages(physical/fabiraction/layout) between the 2 resistors...

Thanks again for the information and time...
 

p+ resistor

Hello bharatsmile,

if I'd worry a lot about screening the resistor from picking up noise from the environment, I'd use a P+ resistor in a separate n-well, and supply the n-well by any fixed voltage with the least noise level (a separate n-well may be supplied by any voltage level between gnd and the highest vdd).
Thanx for your help points! ;-)
 
n+ diffussion

The P+ diffusion resistor is in favor because you can use the surrounding NWELL to isolated against noise.

BUT!! opposite to the former post the NWELL should have potential every time higher than than each of the P+ terminals.

The TC is equal which point to a not verified number from the process. Also the voltage coeffcient is set to zero which is not true. Because the space charge region of the diode the effective diffusion depth varies with voltage. You can have voltage coefficient in the low %/V
 

Yes, rfsystem is right! I forgot to mention this. The n-well voltage level must always be higher than the highest voltage at your imbedded P+ diff. resistor, otherwise this resistor would be paralleled (short-circuited) by the forward biased p+ to n-well diode. So probably you need to bias the n-well to VDD, like the n-wells for (most of) the pMOSfets. In this case you may even use a common n-well for your p+ resistor(s) and those pMOSfets.
 
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