MOS & MOM combination layout

mom capacitor structure

Hello People!

I would like to ask if it's possible to combine in the layout under one cell the Metal On Metal(MOM) Capacitor and MOS capacitor? Because I would like to have in my layout a higher density capacitor using less area.

If it is...is there a way to get a gate oxide capacitor below a MOM capacitor?

Any help would be much appreciated!

Cheers

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Good idea.
And I believe - it will function perfectly on silicon too.
Now, think about LVS tool - does that allow to have two different device recognition shapes overlap and even other problem for device formation if terminal shapes of different devices overlap - although they might belong to different net - I think it will warn/error with illegal devices.

mom+capacitance

hi sat - as far as i know if i'm going to put it in silicon reality there will be no problem....as MOM only consist of Metals from lowest to highest metal...then the MOS only compose of active area and gate oxide...

LVS will not be an issue i guess it's just like putting your MOS under the bunch of metal stripes..

i hope you could give me more ideas...and maybe we can work on it to put them in reality...

cheers

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Hi
I completed a chip a couple of months back with metal over a mos cap using metals 2/3/4 and it worked fine. We didn't have all of the devices to recognise them for lvs but as the capacitances where the same it didn't cause an issue.
If I get some time I'll take a picture of it.
K


Hello People!


I would like to ask if it's possible to combine in the layout under one cell the Metal On Metal(MOM) Capacitor and MOS capacitor? Because I would like to have in my layout a higher density capacitor using less area.

If it is...is there a way to get a gate oxide capacitor below a MOM capacitor?

Any help would be much appreciated!

Cheers

combination layout

hi k_90 - thanks for your input. It would be nice if you can take some pix and post it here.

Again thanks for the input.

cheers

its a poly poly cap but the principle is the same.

Just for understanding and clarity - on what we are trying to achieve - we are trying to make a decoupling cap which will provide us more capacitance per unit area correct?

Please correct me - if I am wrong - I just wrote decap - the reason is I believe MOSCAPs are always decoupling cap - based on PMOSCAP or NMOSCAP it must have one leg [shorted S/D] tied to either VDD or GND. The capacitance varies as the Gate-Voltage varies - offers minimum cap value at channel inversion.

What we lose in this merger - is its pure bidirectional nature of original MOM - and we also lose [nearly] voltage independence [of course when applied plate-voltage difference is much below dielectric breakdown voltage]. As we are trying to achieve larger cap - we will add them in parallel - where one is voltage-dependent in nature.
MOSCAPs are leaky at sub-wavelength nodes [gate leakage current] - no good for low-power application.

We are gonna lose some characteristics - aren't we?

We also prepare to do this these days.AFAIK,the DRC rule will not be met. Of course it will be OK when testing the chip .But the reliability would be a problem in the future .

Guys, if I remember correctly, there is a Philips (now NXP) patent on this structure. This is the reason why the MOS-MOM capacitor is not offered by any foundry as a standard component.

JoannesPaulus said:

Guys, if I remember correctly, there is a Philips (now NXP) patent on this structure. This is the reason why the MOS-MOM capacitor is not offered by any foundry as a standard component.

Click to expand...

Do you have the link on this patent so that we can read and learn more on it.

I saw the Patent for MOM capacitor with Conductive Plate for preventing parasitic capacitance and method of making the same....invented by Man-Chun Hu and Wen Chung Lin from Taipei.


thanks

I would have to look for it...