Continue to Site

Welcome to EDAboard.com

Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.

Register Log in

How to improve bandgap PSRR without changing topology or layout?

Status
Not open for further replies.
W

Warlike

Junior Member level 3
Joined
Dec 6, 2006
Messages
31
Helped
2
Reputation
4
Reaction score
0
Trophy points
1,286
Location
Moscow, Russia
Activity points
1,515
Hello! I designed Bandgap voltage reference. In attachement is PSRR jpeg. Tell me please: does this PSRR normal or bad? Exactly what about 0 dB crossing?

If it's very bad how correct this without topology and layout change? Maybe capacitance at the Vref node?
 

psrr bandgap

Warlike said:
Hello! I designed Bandgap voltage reference. In attachement is PSRR jpeg. Tell me please: does this PSRR normal or bad? Exactly what about 0 dB crossing?

If it's very bad how correct this without topology and layout change? Maybe capacitance at the Vref node?
Click to expand...


yes, it is quite normal graph for PSRR. but maybe you can add a cap at the bandgap output to increase psrr at high frequency.

But if you have power supply filter, let say with cut off frequency 1 MHZ, will be able to solve the problem.
 
how to reduce high frequecy psrr

Not very impressive. If some of your blocks work around 40MHz, and introduce 5mV ripple (which is not uncommon), you will have 30mV error in your reference. If it happens to be an ADC or DAC, this will show up as a huge spur. It's not practical to filter these frequencies on-chip. If you are going to feed the reference current to a PLL you may not have troubles though.
Moreover your supply may come from a switcher whose frequency can be in several MHz.
 
bandgap switching noice

If some of your blocks work around 40MHz, and introduce 5mV ripple (which is not uncommon), you will have 30mV error in your reference. If it happens to be an ADC or DAC, this will show up as a huge spur.
Click to expand...
It's bandgap for set Vos in the LVDS transmitter that switched by 250 MHz clock. Does this PSRR normal for this application or I should correct it/design new BGVR?

It's not practical to filter these frequencies on-chip.
Click to expand...
If it would be separate supply for Bandgap and other blocks would it work good?
 

how much of psrr is good

I don't know what is suited for this application., but you can do some simple math with the current taken by the transmitter, expected routing resistance to convince yourself. The on-chip decap is not going to be so effective even at 250MHz. If you are operating with supply beyond 1.2V, this PSRR looks much lower than what is possible.
Having a separate supply for BGR is nice., but do you have that luxury? See whether you could tune up the PSRR of the BGR before taking such a big decision
 

bandgap pssr

If you are operating with supply beyond 1.2V
Click to expand...
Power supply is 2.5.

Having a separate supply for BGR is nice., but do you have that luxury?
Click to expand...
I don't know yet. Will know soon.

See whether you could tune up the PSRR of the BGR before taking such a big decision
Click to expand...
Yes. Will try.

What is a normal PSRR? Can you give me an example for what I need work?
 

psrr + dac + improving

With 2.5V supply, you should target atleast for 60dB at low frequencies. You should get the specs for the PSRR from the system designers or the one who gave all the other specs of the block to you. See how far you are from the spec and then decide what to do.
 

bandgap psrr

With 2.5V supply, you should target atleast for 60dB at low frequencies.
Click to expand...
Ok. Will target for 60 dB. But what about high frequencies? What is a minimum PSRR? (typicaly)

You should get the specs for the PSRR from the system designers or the one who gave all the other specs of the block to you.
Click to expand...
I'll ask they.

See how far you are from the spec and then decide what to do.
Click to expand...
I think I should improve topology and remake layout. It's not good. But not terrible.
 

psrr bgr

Need to consider the switching regulator on board. It could introduce supply noise up to 1MHz (tens mili-volt).
 

bandgap spur

enlarge your loop gain since the PSRR in low frequency is too low.
 

psrr and bandgap

I had improve my Bandgap. PSRR plot in attachment.

I have some questions.

1) Should PSRR be more smooth?
2) Now PSRR at low frequencies are good. But what about high frequencies? How much should be PSRR at 10 Mhz, at 100 Mhz? In papers I have seen all PSRR plots was from 1 Hz to 1-10 Mhz. Why? There are no ripple at freq. more than 10 Mhz?
 

what do you need to plot to find band gap

If you have a mixed signal chip with a clk freq larger than 1MHz (not too hard to find), then all the switching noise will be coupled to your bandgap. If that's your case then you should definitively improve HF PSRR
 
1.2v 60db psrr

in physical, 0db psrr means the noise will directly feed through to your output. So if the 0-db freq. is in your circuit operating range, this might bw an issue
 

ｂａｎｄｇａｐ　ｐｓｒｒ

Warlike said:
I had improve my Bandgap. PSRR plot in attachment.

I have some questions.

1) Should PSRR be more smooth?
2) Now PSRR at low frequencies are good. But what about high frequencies? How much should be PSRR at 10 Mhz, at 100 Mhz? In papers I have seen all PSRR plots was from 1 Hz to 1-10 Mhz. Why? There are no ripple at freq. more than 10 Mhz?
Click to expand...

This PSRR plot looks very impressive to me
The high frequency supply currents are redirected through the low impedance path through the decaps so it's normally left out as a manageable problem.
If you include some decap and then run the sim, you should see the curve moving down after 100MHz or so
 

    W

    Warlike

    Points: 2
    Helpful Answer Positive Rating
voltage psrr bandgap voltage reference

saro_k_82 said:
The high frequency supply currents are redirected through the low impedance path through the decaps so it's normally left out as a manageable problem.
If you include some decap and then run the sim, you should see the curve moving down after 100MHz or so
Click to expand...

Yes, that's right, adding decoupling caps will lower the high frequency part of the curve.
 
  • Like
Reactions: mirrobbs

    W

    Warlike

    Points: 2
    Helpful Answer Positive Rating
    M

    mirrobbs

    Points: 2
    Helpful Answer Positive Rating
pssr bandgap

PaloAlto said:
saro_k_82 said:
The high frequency supply currents are redirected through the low impedance path through the decaps so it's normally left out as a manageable problem.
If you include some decap and then run the sim, you should see the curve moving down after 100MHz or so
Click to expand...

Yes, that's right, adding decoupling caps will lower the high frequency part of the curve.
Click to expand...
 

Re: Bandgap PSRR

Hi there.
This PSRR plot is really impressive.

Are you usign an opamp to force the deltaVBE or are you using cascoded PMOS and NMOS?

I guess you're using a really high-gain high-bandwidth amp. Can i ask what's the tehcnology and how much quiescent current you are burning on the opamp?

Thanks
 

Re: Bandgap PSRR

This PSRR plot is really impressive.

any body has any idea how to improve PSRR like this?

Thanks
 

Status
Not open for further replies.

Similar threads

Part and Inventory Search

Welcome to EDABoard.com

Sponsor

Back
Top