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in theory you could. it would also make your clock multiplexing scheme a lot simpler - it just won't exist.
but in reality I never saw something like this.
I believe that you want to operate in such a technology that allows you to utilize more logic between flops. with a scan your logic depth is basically one mux.
You circuit may run that fast, but the test machine can't run so fast, because the test machine will give the test patterns through it's I/O pins, such as test_din, test_mode, and the test machine will capture the test_out to compare you circuit shift out with the golden value. So usually, the test mode frequence will mostly depend on the test machine speed, not your circuit.
The maximum shift frequency will depend on what is the maximum peak power, the chip can support.
When you are shifting the data on the scan chain, all the flops in the chains are operational the same time. The peak power requirment goes high, also too much of heat is generated , if you dont account for it the chip will burn up.
In the functional mode , you will never get a chance where all the flops will be operational at the same time...
The maximum shift frequency will depend on what is the maximum peak power, the chip can support.
When you are shifting the data on the scan chain, all the flops in the chains are operational the same time. The peak power requirment goes high, also too much of heat is generated , if you dont account for it the chip will burn up.
In the functional mode , you will never get a chance where all the flops will be operational at the same time...
typically shift frequency is 100Mhz. for above the reasons. If you are running shift clock as a functional frequecy, tester cost will increse because of the clock circuit @ tester.
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