Rule of thumb for Vdsat

Hi all,

From your experience, what is the rule of the thumb of the vdsat value (50mV? 100mv? >100mV?) in analog design?

Thanks

Hi pbs681,

Upto my understanding Vdsat is the min. value of VDS required for strong inversion provided VGS > Vth.

the mathematical equation involves Esat,Leff,Vgseff ...

So to fix this you have u fix paramters associated with it..

or are you asking about drop across individual MOS(This is imported whn stacking is done with low voltage rail)?

Please pardon me if i misunderstood u r Question.

Thanks,

I use devices sized for 150mV to 200mV as a general rule. Usually these are current mirrors. Diff pairs are designed for gm, not vdsat.

There is no single answer to your question. It depends on the circuit goals. For example, if you design current mirrors, or design for high frequency or good THD, then you want bigger Vdsat, like 200mv, 300mv (if you can afford). If you need diff pair, or low power circuits, transistors with better current efficiency, then you design with small Vdsat - in the order of 100mV, 150mV. If you need higher output swing you also will need small Vdsat. If you design for low voltage, Vdd=1v to 2v then you will not be able to use more than 150mV perhaps.
If you don't care about all these things you can find a sweet spot where you get both good frequency response and good current efficiency. And BTW, with modern nm technologies, Vdsat as a design parameter looses sense. For example in 65nm and 45nm when the simulator shows Vdsat=Vgs-Vth=0 you are nowhere close to subthreshold, but rather in moderate inversion. Vdsat of about -100mV is better indication of weak inversion - of course if we believe the models.

It's better to distingush two parameters Vdsat and Vov=Vgs-Vth (overdrive voltage).
Vov shows operation region of MOSFET
Vov~-50mV - weak inversion
Vov~50mV - moderate inversion
Vov~200mV - strong inversion

Vdsat usually slightly lower Vov in strong inversion region and high than Vov in moderate/weak inversion regions. It's never negative.

The prefereble region for current mirror is strong inversion, for diff. pairs and cascode - weak/moderate inversion.

thanks all for the reply!!

sutapanaki said:

... And BTW, with modern nm technologies, Vdsat as a design parameter looses sense. For example in 65nm and 45nm when the simulator shows Vdsat=Vgs-Vth=0 you are nowhere close to subthreshold, but rather in moderate inversion. Vdsat of about -100mV is better indication of weak inversion - of course if we believe the models.

Click to expand...

Does that mean in sub-micron design, if you see your transistor's vgs-vth≤0, there is a good chance that the transistor still operates in moderate inversion instead of weak inversion?

Thanks

yes. Just plot gm/Id vs. Vgs-Vth and you'll see.

sutapanaki said:

yes. Just plot gm/Id vs. Vgs-Vth and you'll see.

Click to expand...

How do you consider what region is weak inversion? When the gm/Id is flat?

Thanks

yes.

Thanks! ^^