Continue to Site

Welcome to EDAboard.com

Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.

Register Log in

how to generate clock signal for ADC & DAC?

Status
Not open for further replies.
L

liletian

Full Member level 6
Joined
Mar 5, 2008
Messages
337
Helped
2
Reputation
4
Reaction score
2
Trophy points
1,298
Activity points
3,790
how to generate a clock signal

Hi Guys
What is the normal way to generate clock signal for ADC? where can I find a complete ADC design circuit where clock signal generation on? I will think to generate clock signal using inverter oscillator and use digital logic to generate other waveform based on this, any suggestions?
Thanks
 


how to generate clock for adc

amol_shah said:
which ADC are you using?
you can use a 555 ckt or you can give the clk through the controller itself

here is a link for interfacing ADC 0808 to 8051 controller, the clock is provided by the controller itself
https://www.dnatechindia.com/index.php/Tutorials/8051-Tutorial/Interfacing-ADC0808-To-8051.html
Click to expand...
I want to make the clock myself so I can integrated it in one chip? I would like the ADC frequecny up to 10MHZ. Any suggestions?
Thanks
 

generate clock

You'd be best off using an external clock generator, even just a simple oscliator.

Generating clocks can be a noisy business
 

adc clock generation

We use pll generate the ADC clock usual. There is the PLL in your product system usual. Did you only design a ADC and it is not in some product ?
 

adc and dac interface with 8051 tutorial

jerryzhao said:
We use pll generate the ADC clock usual. There is the PLL in your product system usual. Did you only design a ADC and it is not in some product ?
Click to expand...
Yes, we do have a PLL in the loop, but the signal I have in PLL is from a inverter oscillator at 2.2GHZ, and the signal I want is a signal at 5-10Mhz and a signal 2.195MHZ, is it possible? should I use digital counter to generate the signal? If possible, could you please decribe it in details?
Thanks a lot
 

Let digital engineer help you. you tell them your timing, they will give you the timing that you needed. Do this timing is easy for a digital engineer.
 

jerryzhao said:
Let digital engineer help you. you tell them your timing, they will give you the timing that you needed. Do this timing is easy for a digital engineer.
Click to expand...
Can you tell me how to do it? I am going to be partly digital guy.
Thanks
 

If you are using microcontroller then you can probably connect your ADC/DAC to the SPI interface of MCU if your ADC/DAC can support SPI interface. Alternatively, you can also use polling method with the normal I/Os to generate clock.
 
Hi Liletian:
I think you know your ADC&DAC timing clearly. Tell your digital engineer the timing spec, you'd better draw a detail timing diagram for digital engineer. I am not digital engineer, I only tell my request to digital engineer in our design team. the timing of digital part generate by digital synthesis.

Added after 7 minutes:

The input of digital block is the PLL's output. I think the digital engineer generate the low speed clock by digital divider.
 

Status
Not open for further replies.

Similar threads

Part and Inventory Search

Welcome to EDABoard.com

Sponsor

Back
Top