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how to define an array in vhdl code

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j hemangini

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vhdl array definition

I want to define an array having values [1,2,3,4,5] etc, and then want access these values one by one . Please tell me how can i define any fixed value array in vhdl code and how can i access values from that array.
Thank you.
 

array in vhdl

The Array declaration type is of the following type:
-------------
TYPE SAMPE_main IS ARRAY (1 to 10) OF INTEGER;
CONSTANT SAMPLE : SAMPLE_main := (1,2,3,4,5,6,7,8,9,10);
------------
In your design,
----------------------------
PROCESS(CLK) THEN
VARIABLE i : INTEGER RANGE 0 TO 10;
BEGIN

IF RISING_EDGE(CLK) THEN
i:=i+1;
IF(i<10) THEN
OUTPUT <= SAMPLE(i);
ELSE
OUTPUT <= SAMPLE(i);
i:=0;
END IF;
END IF;
END PROCESS;

For each clock, every array index value will be accesed and it's being looped. Hope this helps..
 
access arrays in vhdl

Thanks for your reply.
Now i want to know one more thing is that,
if i would like to define an array having values in binary format like
[1001000001 , 1010010011 , 1010000011 , 1010011011]
and also having values in hex like [0x41 , 0x 42 , 0x 43] etc then
how can i define these types of array and how can i access them in vhdl code.

thank you.

Added after 1 hours 18 minutes:

in vhdl code how can i convert a decimal value into binary or hex equivalent ?
 
array vhdl definition

say you have an integer called int1 with range 0 to 255. To convert it into std_logic_vector, you will need a signal say, vec1 : std_logic_vector(7 downto 0). Now use the following for the conversion:
vec1 <= std_logic_vector(conv_unsigned((int1),8 ));

Now say you have a signal say vec2 : std_logic_vector(7 downto 0), to convert it into an interger say int2:
int2 <= conv_integer(unsigned(vec2));


To define an array of std_logic_vector types: you will need a 'type' definition

type my_array is array(3 downto 0) of std_logic_vector(9 downto 0);

then you can declare a signal using that 'type', for example:
mysignal : my_array;

You will have to convert hex into binary before you can use them in vhdl in most cases.
However constant hex values can be assigned to signal using the following
mysignal <= X"41";
Hope it helps
Kr,
Avi
 
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