can LEC read svf file generated by DC

svf lec

I wonder if Cadence LEC can read svf file generated by DC.
If it can, it's convenient.

set flatten model -seq_constant

I think it can't be work, different EDA tool in different company! somebody else can share your experience?

lec svf file

hello wkong_zhu,
I am a frequent user of sign-off tools such as LEC, primetime, Apache RedHawk, Mentor Calibre etc and I set up CAD flows for a medium size ASIC company. I believe sign-off tools need to work independently without getting any hinting information to function.

I have seen some users ask me about supporting svf file generated by DC. It can be done by some scripting. But this is not good. There are some cases where DC has created a design bug and the svf file has the same bug in it. You can see a popular thread below, where the dangers of passing information from DC to Equivalency Checking tools were discussed . . .

https://www.deepchip.com/items/0464-04.html

Therefore, I believe using an svf file is not good. Usually what I have seen is that you can always verify the design with LEC but will require some setting in LEC.

If you have challenges verifying your design then I recommend you contact a Cadence AE supporting LEC.

-- Adam

dc command for write svf

Adam:
Thanks for your kindly reply.
By now, I just use LEC directly, and never use svf files.
LEC is much powerful, just some settings are enough to compare all the designs.
But, I faced some problems with LEC. When the logic cone is very complicated, the LEC tools will compare with abort. How can I force LEC to go on compare until it come up with the answer yes or no. I think LEC tools can not deal with too much complex bool functions.
Would you give me some hints?
Thanks again.

set flatten model multiplier

I was doing LEC last a few days, here is my 2cents.
In most case, with set flatten model -seq_constant option, LEC works very well.
But in one block, I have to use -noseq_feedback_constant.

Right now , I use a script to generate a constraint file and run with -noseq_feedback_constant option.
The script will call up formality , and generate a txt file of svf , then I will
grep all those guide_constant_reg line in the txt . (this sets the constant regs)

But I still have a 24x24 multiplier haven't verified yet.
(Based on web informations, formality should able to verify 64x64 multiplier)

you can set verify effect high to force the LEC not abort.

dc formality svf flow

Can I have simple script file for running Formality.

dc_shell-t svf

Adam.Yakuvitz said:

hello wkong_zhu,
. I believe sign-off tools need to work independently without getting any hinting information to function.

I have seen some users ask me about supporting svf file generated by DC. It can be done by some scripting. But this is not good. There are some cases where DC has created a design bug and the svf file has the same bug in it. You can see a popular thread below, where the dangers of passing information from DC to Equivalency Checking tools were discussed . . .

https://www.deepchip.com/items/0464-04.html

-- Adam

Click to expand...

I can't agree any more.

formality set svf

Hi Man,
As of now LEC doen't read SVF file from DC.Its not a correct approach to verify design using site files.

Regarding aborts use analyze abort -compare ,compare -thread 2 or run partition command in your flow.

Let me know if any help needed.

Regards

Re: lec svf file

Adam.Yakuvitz said:

hello wkong_zhu,
I am a frequent user of sign-off tools such as LEC, primetime, Apache RedHawk, Mentor Calibre etc and I set up CAD flows for a medium size ASIC company. I believe sign-off tools need to work independently without getting any hinting information to function.
........................................................

Cann't agree you more.

Click to expand...