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free high level synthesizers (systemc)

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salma ali bakr

salma ali bakr

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Hi,

Is there any free high level synthesizer to convert systemc to vhdl or verilog or netlist or any sort of hardware description ?!

Thanks in advance,
Salma :)
 

Hi Salma,
Try this one:
**broken link removed**

Advares !
 
thanks a lot
but that performs the opposite of what i want...it transforms vhdl to systemc!!
 

I think there is no free high level synthesizer tool available because if we (the FPGA community) want to build FPGA synthesis tools we need to know the specification of the bitfiles that are used to "configure" the FPGA's with the application you develop in for instance SystemC. This specifications are not available from the FPGA manufacturers...
 
hello folks,
i want to mention that Catapult from mentor synthesize only C/C++ to vhdl or verilog or systemC
 
Catapult is not free anyway. I don't think there is anything like this you can get for free.
 
mobile-it said:
I think there is no free high level synthesizer tool available because if we (the FPGA community) want to build FPGA synthesis tools we need to know the specification of the bitfiles that are used to "configure" the FPGA's with the application you develop in for instance SystemC. This specifications are not available from the FPGA manufacturers...
Click to expand...

but if the design is transferred to register level and modeled in, for instance, xilinx system generator...then the configuring of the FPGA is very close! in system generator, you can generate the HDL netlist, then take the project to ISE and download it on the FPGA (with all the IOs specified in system generator)...
 

salma ali bakr said:
mobile-it said:
I think there is no free high level synthesizer tool available because if we (the FPGA community) want to build FPGA synthesis tools we need to know the specification of the bitfiles that are used to "configure" the FPGA's with the application you develop in for instance SystemC. This specifications are not available from the FPGA manufacturers...
Click to expand...

but if the design is transferred to register level and modeled in, for instance, xilinx system generator...then the configuring of the FPGA is very close! in system generator, you can generate the HDL netlist, then take the project to ISE and download it on the FPGA (with all the IOs specified in system generator)...
Click to expand...
Hi Salma,
Hi all,
I think it is a good idea but I find that lot of tools from different vendors are used and it may happen incompatibility between them in some cases . This if you dont consider the misalignement introduced by the SystemC-VHDL compiler between the original discription and the generated VHDL.

Please if anyone has tested this technique let us know about its efficiency.
 

ROCCC
its free opensource
c -> hdl converter
try it
 

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