Continue to Site

Welcome to EDAboard.com

Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.

Register Log in

Challenging Problem in VHDL Design : Password Attacker

Status
Not open for further replies.
G

govandi999

Newbie level 4
Joined
Jun 10, 2005
Messages
5
Helped
1
Reputation
2
Reaction score
0
Trophy points
1,281
Activity points
1,331
vhdl elsif hex

In this design, we have to capture the behavior of a password attacking mechanism (Bruteforce) by writing a behavioral VHDL code.

Mechanism

We have an input "DATA" of size 8-bit. The password would be somewhere between 00 to FF (hex). We will set the input at say 1C (hEX) . The attack will start from this input say 1C and it will scan through upto FF. We have another input "START". It means when START ='1' then the password attacking begins. An 8-bit password is already stored in a variable inside the code. If the system finds the correct password then it will stop at that number. If not, then it stops at FF (hex).

If someone can initiate the design for this problem. Pl. post it here
 

design password

Check out this one!
Code: 
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;

entity passwd is
  
  port (
    clk     : in  std_logic;
    rst_n   : in  std_logic;
    data    : in  std_logic_vector(7 downto 0);
    start   : in  std_logic;
    pass_wd : out std_logic_vector(7 downto 0));

end passwd;

architecture behave of passwd is
signal pass_word : std_logic_vector(7 downto 0) := to_stdlogicvector(x"AB");
signal pass_cnt : std_logic_vector(7 downto 0);
signal start_d : std_logic;

begin  -- behave
 process (clk, rst_n)
 begin  -- process
   if rst_n = '0' then                  -- asynchronous reset (active low)
     start_d <= '0';
     pass_cnt <= (others => '0');
   elsif clk'event and clk = '1' then   -- rising clock edge
     start_d <= start;
     if (start_d = '0' and start = '1') then
       pass_cnt <= data;
     elsif (pass_cnt != passwd or pass_cnt != (others=> '1')) then
       pass_cnt <= pass_cnt + 1;
     end if;
   end if;
 end process;
end behave;
 

challenging vhdl problems

I think you missed out the condition when (start_d = '0' AND start = '0'). Please in consider this condition as well, else the machine will start right after reset.


nand_gates said:
Check out this one!
Code: 
library ieee;
......
     if (start_d = '0' and start = '1') then
       pass_cnt <= data;
     elsif (pass_cnt != passwd or pass_cnt != (others=> '1')) then
       pass_cnt <= pass_cnt + 1;
     end if;
......
Click to expand...
 

password attacker vhdl

I tried to run the VHDL code as provided by our friend but it gives error while synthesizing (compiling)


signal pass_word : std_logic_vector(7 downto 0) := to_stdlogicvector(x"AB");
to_stdlogicvector has two or more possible definitions in this scope. For example, parameter 1 (string value) can be: std_ulogic_vector or BIT_VECTOR


elsif (pass_cnt != passwd or pass_cnt != (others=> '1')) then

parse error, unexpected EQ
 

    G

    govandi999

    Points: 2
    Helpful Answer Positive Rating
to_stdlogicvector

Here is the corrected code.
Use -explicit switch for vcom
Code: 
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity passwd is
  
  port (
    clk     : in  std_logic;
    rst_n   : in  std_logic;
    data    : in  std_logic_vector(7 downto 0);
    start   : in  std_logic;
    pass_wd : out std_logic_vector(7 downto 0));

end passwd;

architecture behave of passwd is
signal pass_word : std_logic_vector(7 downto 0) := "10101010";
signal pass_cnt : std_logic_vector(7 downto 0);
signal start_d : std_logic;

begin  -- behave
 process (clk, rst_n)
 begin  -- process
   if rst_n = '0' then                  -- asynchronous reset (active low)
     start_d <= '0';
     pass_cnt <= (others => '0');
   elsif clk'event and clk = '1' then   -- rising clock edge
     start_d <= start;
     if (start_d = '0' and start = '1') then
       pass_cnt <= data;
     elsif ((pass_cnt /= pass_word) or (pass_cnt /= "11111111")) then
       pass_cnt <= pass_cnt + '1';
     end if;
   end if;
 end process;
end behave;
 

vhdl design problems

Although the password is error free now. But It does not do what is required as per the problem statement.

1. It doesnot give any output.
For example when the password is found what is the value of the output
pass_wd.If yourun the curent VHDL code, it doesnot give any output

2. Also the initial value`for starting is 1C, it should start scanning from 1C and
continue until it finds the password,if it finds the password, it should give an
output equal to the password else it should continue scanning till FF.

Pl. incorporate these changes in the code.

Rest is OK.
 

    G

    govandi999

    Points: 2
    Helpful Answer Positive Rating
Status
Not open for further replies.

Similar threads

Part and Inventory Search

Welcome to EDABoard.com

Sponsor

Back
Top