best way to learn functional verification ?

hi all

I need to know the best way to learn functional verification .

Through web browsing i reached this conclusion (correct me if i am wrong)

functional verification has different technologies

1]Assertion based verification : where u write assertions into ur vhdl/verilog code

using either psl , ovl or system verilog then run a simulator as modelsim to verify

2]Coverage driven verification
3]constrained random verification

actually i dunno how to start . do i have to learn ABV first or what can i do ?

i need to ask a few questions :-

1]which above technology does writing testbenches belong to ?
2]Are languages as vera ,e ,system verilog restricted to ABV or they r used elsewhere
i 'm really confused , plz help

As with any complex topic, you need to practice to become expert and have a strong hold. So my recommendation is to start writing testbenches (in whichever language you can) and slowly pick up advanced topics like ABV, SV etc.

BTW, we offer a course on exactly this topic - "Comprehensive Functional Verification" - if you are based in Bangalore you can attend this. Send an email to cvc.training @ gmail.com or ajeetha @ gmail.com if you are interested.

We are likely to have a class during June 1st or 2nd week. Look at:

http://www.noveldv.com/pub_docs/cvc_cfv_profile.pdf

For full details, a brief intro is below:

Overview
Functional Verification is one of the most time-consuming processes
in ASIC design cycle; yet a structured introductory course/training/education
on this topic is often missing. Neither the educational institutes offer this nor
there are vendors offering such training. While several language specific
courses are offered by EDA vendors, a comprehensive training on
fundamentals of functional verification is lacking. CFV course gives you an
in-depth introduction to the different aspects of functional verification
including different testbench architectures, their relative merits, demerits,
areas of application of each architecture etc. CFV then delves into what is a
good testbench, and elements of a modern day testbench. It covers all
aspects of functional verification ranging from verification architecture to
building testbenches, gate level simulation and various technologies used in
verification such as simulation, formal, emulation
Objectives

To explore what is verification and why it is needed and how it is
achieved.

To examine the different testbench architectures available

To explain key features of a good testbench

To suggest widely used guidelines and need for a methodology

To elaborate on all the different terminologies, buzz words used in
the industry

To introduce different stages in functional verification such as RTL
simulation, gate level simulation, emulation etc. and to address the
challenges in each one of them