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Quick Verilog Questions

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easytarget

easytarget

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Hi,

I'm learning Verilog and I have questions, I'll put them in this thread and your help is appreciated, questions in red are still not aswered, questions in blue are answered. I'll add the answers in this post so others can easily find them.

1- What does it mean when a variable is preceded by ` like this:

wire [`address_size-1:0] addr

Anwer (thanks to vomit):
`address_size is a macro.

2- Can you please explain this:

`define size (1 << `set_size)

Thanks for your help
 

These 2 questions are related: the address_size is not a variable but a macro. Where you use it you have to precede it by a tick mark.
What is a macro ?

A macro is a literal name used in a program that is substituted by some value before the program is compiled. Macros are useful as an alias without using program resources. They are not variables, so you can not assign a value to a macro from within a program. Almost all modern languages, including Verilog, support macro definition.
Macros in Verilog

Macros in Verilog are specified by using `define compiler directive. Here is an example:
`define MY_DELAY 2
...
r1 = #`MY_DELAY 1'b1;
Click to expand...
 

    easytarget

    easytarget

    Points: 2
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Thanks vomit, there was no `define statement in that file, I guess it can be in another file.
I still don't know the answer to the other question, what's does this (1 << `set_size) do?
 

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