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About Charge Pump and VCO

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mouzid

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Dear all,
I have 2 questions regarding the Charge Pump and a simple filter in a PLL.
1- In the documentation the UP and Down signals comming from a conventional PFD composed of 2 DFF and an AND gate are connected respectively to the UP and Down input of the CP (see figure).
Dont we need an inverter to insert between UP (of PFD) and UP (of the CP) ?

2- Is the role of the filter to ensure that the VCO tuning volage is in the appropriate range in which the VCO oscillate ?

What are the parameters to use do dertermine the capacitance and the resistance of the filter.
I guess the Frequency of the PFD and the Voltage Tuning range

Please help.
 

Hi Mouzid, please do a google search for "Fuding Ge pll thesis"

There you will get this thesis. Yes the loop filter needs to be designed so that the PLL locks to the input frequencies.You will find the standard design equations in any design book.


Amarnath
 

    M

    mouzid

    Points: 2
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mouzid said:
Dear all,
I have 2 questions regarding the Charge Pump and a simple filter in a PLL.
1- In the documentation the UP and Down signals comming from a conventional PFD composed of 2 DFF and an AND gate are connected respectively to the UP and Down input of the CP (see figure).
Dont we need an inverter to insert between UP (of PFD) and UP (of the CP) ?

2- Is the role of the filter to ensure that the VCO tuning volage is in the appropriate range in which the VCO oscillate ?

What are the parameters to use do dertermine the capacitance and the resistance of the filter.
I guess the Frequency of the PFD and the Voltage Tuning range

Please help.
Click to expand...

Hi,mouzid
1. The up signal would be inverted to control the PMOS.
2. This is a complex problem. The function of the loop filter is to tune the performance of the whole PLL loop. For example, it can filter the high frequency component of the charge pump current and keep the control voltage of the VCO near to the DC component, this helps to reduce the VCO ouput jitter. It can also tune the loop bandwidth, damping factor, etc.

Hope to be helpful.
 

    M

    mouzid

    Points: 2
    Helpful Answer Positive Rating
amarnath said:
Hi Mouzid, please do a google search for "Fuding Ge pll thesis"

There you will get this thesis. Yes the loop filter needs to be designed so that the PLL locks to the input frequencies.You will find the standard design equations in any design book.


Amarnath
Click to expand...

I searched for the Fuding Ge's thesis but I couldn't find it. Can anybady upload it for me ?

Thanks.
 

Please read this book. It's very good for PLL design.
 

    M

    mouzid

    Points: 2
    Helpful Answer Positive Rating
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