twiieeet
Newbie level 4
cmos current reference
Hello,
I am trying to design a CMOS current reference. I found the following paper:
All CMOS Temperature, Supply Voltage and Process Independent Current Reference
WANG Yi*ˈ He Lenainˈ Yan Xiaolang
On the first page, right column, the writer explains M10-M12 forms a feedback branch. From the current references I have studied until now, I would expect the gate of M7 to be connected to the drain of M3 for to close the loop. I don't see how the feedback works with M10-M12.
The author refers to a another paper of him that was published in Chinese Journal of Semiconductors:
Wang Yi, He Le’nian, Yan Xiaolang, 30nA temperature-independent CMOS current and its application in an LDO, Chinese Journal of Semiconductors. 2006, 27 (9): 1657-1662.
Unfortunately I was unable to get this paper, and I'm afraid that I would only find out that's it written in Chinese, which I can't read.
Does somebody here understand that circuit? If yes, please explain me ...
Hello,
I am trying to design a CMOS current reference. I found the following paper:
All CMOS Temperature, Supply Voltage and Process Independent Current Reference
WANG Yi*ˈ He Lenainˈ Yan Xiaolang
On the first page, right column, the writer explains M10-M12 forms a feedback branch. From the current references I have studied until now, I would expect the gate of M7 to be connected to the drain of M3 for to close the loop. I don't see how the feedback works with M10-M12.
The author refers to a another paper of him that was published in Chinese Journal of Semiconductors:
Wang Yi, He Le’nian, Yan Xiaolang, 30nA temperature-independent CMOS current and its application in an LDO, Chinese Journal of Semiconductors. 2006, 27 (9): 1657-1662.
Unfortunately I was unable to get this paper, and I'm afraid that I would only find out that's it written in Chinese, which I can't read.
Does somebody here understand that circuit? If yes, please explain me ...